AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 177

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Receiver Overrun
Parity Error
Receiver Framing
Error
6071A–ATARM–28-Oct-04
Figure 67. Receiver Ready
If DBGU_RHR has not been read by the software (or the Peripheral Data Controller) since the
last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in
DBGU_SR is set. OVRE is cleared when the software writes the control register DBGU_CR
with the bit RSTSTA (Reset Status) at 1.
Figure 68. Receiver Overrun
Each time a character is received, the receiver calculates the parity of the received data bits,
in accordance with the field PAR in DBGU_MR. It then compares the result with the received
parity bit. If different, the parity error bit PARE in DBGU_SR is set at the same time the
RXRDY is set. The parity bit is cleared when the control register DBGU_CR is written with the
bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status com-
mand is written, the PARE bit remains at 1.
Figure 69. Parity Error
When a start bit is detected, it generates a character reception when all the data bits have
been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing
Error) bit in DBGU_SR is set at the same time the RXRDY bit is set. The bit FRAME remains
high until the control register DBGU_CR is written with the bit RSTSTA at 1.
Figure 70. Receiver Framing Error
RXRDY
RXRDY
RXRDY
OVRE
DRXD
PARE
FRAME
DRXD
DRXD
RXRDY
DRXD
S
S
S
S
D0
D0
D0
D0
D1
D1
D1
D1
D2
D2
D2
D2
D3
D3
D3
D4
D4
D3
D5
D5
D4
D4
D6
D6
D5
D5
D7
D7
D6
D6
AT91SAM7S32 Preliminary
P
P
Wrong Parity Bit
D7
D7
stop
P
P
Detected at 0
S
S
Stop Bit
stop
stop
Read DBGU_RHR
D0
D0
D1
D1
D2
D2
D3
D3
RSTSTA
RSTSTA
D4
D4
D5
D5
D6
D6
D7
D7
P
P
stop
RSTSTA
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