AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 384
AT91SAM7S32-AI
Manufacturer Part Number
AT91SAM7S32-AI
Description
AT91 ARM Thumb-based Microcontrollers
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT91SAM7S32-AI.pdf
(446 pages)
- Current page: 384 of 446
- Download datasheet (3Mb)
PWM Channel Mode Register
Register Name: PWM_CMRx
Access Type:
• CPRE: Channel Pre-scaler
• CALG: Channel Alignment
0 = The period is left aligned.
1 = The period is center aligned.
• CPOL: Channel Polarity
0 = The output waveform starts at a low level.
1 = The output waveform starts at a high level.
• CPD: Channel Update Period
0 = Writing to the PWM_CUPDx will modify the duty cycle at the next period start event.
1 = Writing to the PWM_CUPDx will modify the period at the next period start event.
384
0
0
0
0
0
0
0
0
1
1
1
1
1
31
23
15
–
–
–
7
–
AT91SAM7S32 Preliminary
Read/Write
0
0
0
0
1
1
1
1
0
0
0
0
1
30
22
14
–
–
–
6
–
CPRE
Other
0
0
1
1
0
0
1
1
0
0
1
1
0
29
21
13
–
–
–
5
–
0
1
0
1
0
1
0
1
0
1
0
1
0
28
20
12
–
–
–
4
–
MCK
MCK/2
MCK/4
MCK/8
MCK/16
MCK/32
MCK/64
MCK/128
MCK/256
MCK/512
MCK/1024
CLKA
CLKB
Reserved
27
19
11
–
–
–
3
Channel Pre-scaler
CPD
26
18
10
–
–
2
CPRE
CPOL
25
17
–
–
9
1
6071A–ATARM–28-Oct-04
CALG
24
16
–
–
8
0
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