AT91SAM7S32-AI ATMEL [ATMEL Corporation], AT91SAM7S32-AI Datasheet - Page 343

• Manufacturer Part Number: AT91SAM7S32-AI
• Description: AT91 ARM Thumb-based Microcontrollers
• Manufacturer: ATMEL [ATMEL Corporation]

Clock Selection
Clock Control
6071A–ATARM–28-Oct-04
At block level, input clock signals of each channel can either be connected to the external
inputs TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signals TIOA0 or
TIOA1 for chaining by programming the TC_BMR (Block Mode). See Figure 149.
Each channel can independently select an internal or external clock source for its counter:
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•
This selection is made by the TCCLKS bits in the TC Channel Mode Register.
The selected clock can be inverted with the CLKI bit in TC_CMR. This allows counting on the
opposite edges of the clock.
The burst function allows the clock to be validated when an external signal is high. The
BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2).
Note:
Figure 149. Clock Selection
The clock of each counter can be controlled in two different ways: it can be enabled/disabled
and started/stopped. See Figure 150.
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•
Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3,
TIMER_CLOCK4, TIMER_CLOCK5
External clock signals: XC0, XC1 or XC2
The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS
commands in the Control Register. In Capture Mode it can be disabled by an RB load
event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC
Compare event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop
actions have no effect: only a CLKEN command in the Control Register can re-enable the
clock. When the clock is enabled, the CLKSTA bit is set in the Status Register.
The clock can also be started or stopped: a trigger (software, synchro, external or
compare) always starts the clock. The clock can be stopped by an RB load event in
Capture Mode (LDBSTOP = 1 in TC_CMR) or a RC compare event in Waveform Mode
In all cases, if an external clock is used, the duration of each of its levels must be longer than the
master clock period. The external clock frequency must be at least 2.5 times lower than the
master clock
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
1
TCCLKS
BURST
AT91SAM7S32 Preliminary
CLKI
Selected
Clock
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