AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 143

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

19.7.2
Name:
Address:
Access:
This register can only be written if the WPEN bit is cleared in the
• SLOT_CYCLE: Maximum Bus Grant Duration for Masters
When SLOT_CYCLE AHB clock cycles have elapsed since the last arbitration, a new arbitration takes place so as to let an
other master access this slave. If an other master is requesting the slave bus, then the current master burst is broken.
If SLOT_CYCLE = 0, the Slot Cycle Limit feature is disabled and bursts always complete unless broken according to the
ULBT.
This limit has been placed in order to enforce arbitration so as to meet potential latency constraints of masters waiting for
slave access or in the particular case of a master performing back to back undefined length bursts indefinitely freezing the
arbitration.
This limit must not be small. Unreasonably small values break every burst and the Bus Matrix arbitrates without performing
any data transfer. The default maximum value is usually an optimal conservative choice.
In most cases this feature is not needed and should be disabled for power saving.
See
• DEFMSTR_TYPE: Default Master Type
0: No Default Master
At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.
This results in a one clock cycle latency for the first access of a burst transfer or for a single access.
1: Last Default Master
At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master
having accessed it.
This results in not having one clock cycle latency when the last master tries to access the slave again.
2: Fixed Default Master
At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the
number that has been written in the FIXED_DEFMSTR field.
This results in not having one clock cycle latency when the fixed master tries to access the slave again.
6438F–ATARM–21-Jun-10
“Slot Cycle Limit Arbitration” on page 137
31
23
15
–
–
–
7
Bus Matrix Slave Configuration Registers
MATRIX_SCFG0...MATRIX_SCFG7
0xFFFFEA40
Read-write
30
22
14
–
–
–
6
29
21
13
–
–
5
for details.
28
20
12
–
–
4
FIXED_DEFMSTR
SLOT_CYCLE
“Write Protect Mode
27
19
11
–
–
3
26
18
10
–
–
2
Register”.
AT91SAM9G45
25
17
–
9
–
1
DEFMSTR_TYPE
SLOT_CYCLE
24
16
–
8
0
143