AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 833

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

38.5.6
Figure 38-6. Example of DMA Chained List:
833
(Current Transfer Descriptor)
UDPHS Next Descriptor
DMA Channel Address
DMA Channel Control
UDPHS Registers
Memory Area
Data Buff 1
Data Buff 2
Data Buff 3
AT91SAM9G45
Transfer With DMA
USB packets of any length may be transferred when required by the UDPHS Device. These
transfers always feature sequential addressing.
Packet data AHB bursts may be locked on a DMA buffer basis for drastic overall AHB bus band-
width performance boost with paged memories. These clock-cycle consuming memory row (or
bank) changes will then likely not occur, or occur only once instead of dozens times, during a
single big USB packet DMA transfer in case another AHB master addresses the memory. This
means up to 128-word single-cycle unbroken AHB bursts for Bulk endpoints and 256-word sin-
gle-cycle unbroken bursts for isochronous endpoints. This maximum burst length is then
c o n t r o l l e d b y t h e l o w e s t p r o g r a m m e d U S B e n d p o i n t s i z e ( E P T _ S I Z E b i t i n t h e
U D P H S _ E P T C F G x r e g i s t e r ) a n d D M A S i z e ( B U F F _ L E N G T H b i t i n t h e
UDPHS_DMACONTROLx register).
The USB 2.0 device average throughput may be up to nearly 60 MBytes. Its internal slave aver-
age access latency decreases as burst length increases due to the 0 wait-state side effect of
unchanged endpoints. If at least 0 wait-state word burst capability is also provided by the exter-
nal DMA AHB bus slaves, each of both DMA AHB busses need less than 50% bandwidth
allocation for full USB 2.0 bandwidth usage at 30 MHz, and less than 25% at 60 MHz.
The UDPHS DMA Channel Transfer Descriptor is described in
Descriptor” on page
Note: In case of debug, be careful to address the DMA to an SRAM address even if a remap is
done.
Next Descriptor Address
DMA Channel Address
DMA Channel Control
Transfer Descriptor
887.
Next Descriptor Address
DMA Channel Address
DMA Channel Control
Transfer Descriptor
Next Descriptor Address
DMA Channel Address
“UDPHS DMA Channel Transfer
DMA Channel Control
Transfer Descriptor
6438F–ATARM–21-Jun-10
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