AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 308
![KIT EVAL FOR AT91SAM9G45](/photos/9/26/92642/at91sam9g45-ekes_sml.jpg)
AT91SAM9G45-EKES
Manufacturer Part Number
AT91SAM9G45-EKES
Description
KIT EVAL FOR AT91SAM9G45
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91SAM9G45-EKES.pdf
(56 pages)
2.AT91SAM9G45-EKES.pdf
(1218 pages)
3.AT91SAM9G45-EKES.pdf
(66 pages)
Specifications of AT91SAM9G45-EKES
Contents
Board
Processor To Be Evaluated
SAM9G45
Data Bus Width
32 bit
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
- 10 C
Operating Supply Voltage
1.8 V to 3.3 V
For Use With/related Products
AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4626953
- Current page: 308 of 1218
- Download datasheet (19Mb)
25.10 Clock Switching Details
25.10.1
308
AT91SAM9G45
Master Clock Switching Timings
Table 25-1
selected clock to another one. This is in the event that the prescaler is de-activated. When the
prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be
added.
Table 25-1.
To
Main Clock
SLCK
PLLA Clock
Peripheral clock 4 is disabled.
write_register(PMC_PCDR,0x00000010)
From
gives the worst case timings required for the Master Clock to switch from one
Clock Switching Timings (Worst Case)
PLLACOUNT x SLCK +
0.5 x Main Clock +
0.5 x Main Clock +
2.5 x PLLAx Clock
Main Clock
4.5 x SLCK
4 x SLCK +
–
PLLACOUNT x SLCK
2.5 x PLLA Clock +
2.5 x Main Clock
4 x SLCK +
5 x SLCK +
SLCK
–
PLLACOUNT x SLCK
2.5 x PLLA Clock +
3 x PLLA Clock +
3 x PLLA Clock +
1 x Main Clock
6438F–ATARM–21-Jun-10
PLLA Clock
4 x SLCK +
4 x SLCK +
5 x SLCK
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