AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 458

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

30.4.5
30.4.6
30.4.7
458
AT91SAM9G45
Synchronous Data Output
Multi Drive Control (Open Drain)
Output Line Timings
The results of these write operations are detected in PIO_OSR (Output Status Register). When
a bit in this register is at 0, the corresponding I/O line is used as an input only. When the bit is at
1, the corresponding I/O line is driven by the PIO controller.
The level driven on an I/O line can be determined by writing in PIO_SODR (Set Output Data
Register) and PIO_CODR (Clear Output Data Register). These write operations respectively set
and clear PIO_ODSR (Output Data Status Register), which represents the data driven on the I/O
lines. Writing in PIO_OER and PIO_ODR manages PIO_OSR whether the pin is configured to
be controlled by the PIO controller or assigned to a peripheral function. This enables configura-
tion of the I/O line prior to setting it to be managed by the PIO Controller.
Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it
defines the first level driven on the I/O line.
Controlling all parallel busses using several PIOs requires two successive write operations in the
PIO_SODR and PIO_CODR registers. This may lead to unexpected transient values. The PIO
controller offers a direct control of PIO outputs by single write access to PIO_ODSR (Output
Data Status Register). Only bits unmasked by PIO_OWSR (Output Write Status Register) are
written. The mask bits in the PIO_OWSR are set by writing to PIO_OWER (Output Write Enable
Register) and cleared by writing to PIO_OWDR (Output Write Disable Register).
After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at
0x0.
Each I/O can be independently programmed in Open Drain by using the Multi Drive feature. This
feature permits several drivers to be connected on the I/O line which is driven low only by each
device. An external pull-up resistor (or enabling of the internal one) is generally required to guar-
antee a high level on the line.
The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and
PIO_MDDR (Multi-driver Disable Register). The Multi Drive can be selected whether the I/O line
is controlled by the PIO controller or assigned to a peripheral function. PIO_MDSR (Multi-driver
Status Register) indicates the pins that are configured to support external drivers.
After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0.
Figure 30-4
directly writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is
set.
Figure 30-4
shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by
also shows when the feedback in PIO_PDSR is available.
6438F–ATARM–21-Jun-10