AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 997

KIT EVAL FOR AT91SAM9G45

AT91SAM9G45-EKES

Manufacturer Part Number
AT91SAM9G45-EKES
Description
KIT EVAL FOR AT91SAM9G45
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr

Specifications of AT91SAM9G45-EKES

Contents
Board
Processor To Be Evaluated
SAM9G45
Data Bus Width
32 bit
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
- 10 C
Operating Supply Voltage
1.8 V to 3.3 V
For Use With/related Products
AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4626953
Figure 41-13. Multi-buffer Transfer with Source Address Auto-reloaded and Contiguous Destination Address
6438F–ATARM–21-Jun-10
Address of
Source Layer
The transfer is similar to that shown in
The DMAC Transfer flow is shown in
b. If the buffer complete interrupt is masked (DMAC_EBCIMR.BTC[x] = ‘1’, where x is
SADDR
automatic transfer mode bit should remain enabled to keep the DMAC in Row 11 as
shown in
the channel number) then hardware does not stall until it detects a write to the buf-
fer transfer completed interrupt enable register but starts the next buffer transfer
immediately. In this case software must clear the automatic mode bit,
DMAC_CTRLBx.AUTO, to put the device into ROW 1 of
before the last buffer of the DMAC transfer has completed.
Source Buffers
Table 41-2 on page
Figure 41-14 on page
Buffer0
Buffer2
Buffer1
Figure 41-13 on page
982.
Destination Buffers
DADDR(0)
DADDR(1)
DADDR(2)
Destination Layer
998.
Address of
997.
Table 41-2 on page 982
AT91SAM9G45
997

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