AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 261

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

22.7.2
Name:
Access:
Reset:
This register can only be written if the bit WPEN is cleared in
• COUNT: DDRSDRC Refresh Timer Count
This 12-bit field is loaded into a timer which generates the refresh pulse. Each time the refresh pulse is generated, a refresh
sequence is initiated.
SDRAM devices require a refresh of all rows every 64 ms. The value to be loaded depends on the DDRSDRC clock fre-
quency (MCK: Master Clock) and the number of rows in the device.
For example, for an SDRAM with 8192 rows and a 100 MHz Master clock, the value of Refresh Timer Count bit is pro-
grammed: (((64 x 10
6438F–ATARM–21-Jun-10
31
23
15
–
–
–
7
DDRSDRC Refresh Timer Register
-3
)/8192) x100 x10
30
22
14
DDRSDRC_RTR
Read-write
See
–
–
–
6
Table 22-9
29
21
13
–
–
–
5
6
= 781 or 0x030D.
28
20
12
–
–
–
4
COUNT
“DDRSDRC Write Protect Mode Register” on page
27
19
11
–
–
3
26
18
10
–
–
2
COUNT
AT91SAM9G45
25
17
–
–
9
1
275.
24
16
–
–
8
0
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