AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 906

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

39.5.1
Register Name:
Access Type:
Reset Value:
• HSYNC_POL: Horizontal Synchronization Polarity
0: HSYNC active high.
1: HSYNC active low.
• VSYNC_POL: Vertical Synchronization Polarity
0: VSYNC active high.
1: VSYNC active low.
• PIXCLK_POL: Pixel Clock Polarity
0: Data is sampled on rising edge of pixel clock.
1: Data is sampled on falling edge of pixel clock.
• EMB_SYNC: Embedded Synchronization
0: Synchronization by HSYNC, VSYNC.
1: Synchronization by embedded synchronization sequence SAV/EAV.
• CRC_SYNC: Embedded Synchronization Correction
0: No CRC correction is performed on embedded synchronization.
1: CRC correction is performed. if the correction is not possible, the current frame is discarded and the CRC_ERR is set in
the status register.
• FRATE: Frame Rate [0..7]
0: All the frames are captured, else one frame every FRATE+1 is captured.
• DISCR: Disable Codec Request
0 = Codec datapath DMA interface requires a request to restart.
1 = Codec datapath DMA automatically restarts.
6438F–ATARM–21-Jun-10
CRC_SYNC
31
23
15
–
7
ISI Configuration 1 Register
EMB_SYNC
30
22
14
6
ISI_CFG1
Read-write
0x00000000
THMASK
29
21
13
5
–
PIXCLK_POL
FULL
28
20
12
4
SFD
SLD
VSYNC_POL
DISCR
27
19
11
3
HSYNC_POL
26
18
10
2
AT91SAM9G45
FRATE
25
17
9
1
–
24
16
8
0
–
906