AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 434

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

29.7.3.7
29.7.3.8
434
AT91SAM9G45
Transfer Size
SPI Direct Access Memory Controller (DMAC)
ever the SPI still controls the number of bits (8 to16) to be transferred through MISO and MOSI
lines with the chip select configuration registers. This is not the optimal means in term of mem-
ory size for the buffers, but it provides a very effective means to exchange data with several
peripherals without any intervention of the processor.
Depending on the data size to transmit, from 8 to 16 bits, the PDC manages automatically the
type of pointer's size it has to point to. The PDC will perform the following transfer size depend-
ing on the mode and number of bits per data.
Fixed Mode:
Variable Mode:
In variable Mode, PDC Pointer Address = Address +4 bytes and PDC Counter = Counter - 1 for
8 to 16-bit transfer size. When using the PDC, the TDRE and RDRF flags are handled by the
PDC, thus the user’s application does not have to check those bits. Only End of RX Buffer
(ENDRX), End of TX Buffer (ENDTX), Buffer Full (RXBUFF), TX Buffer Empty (TXBUFE) are
significant. For further details about the Peripheral DMA Controller and user interface, refer to
the PDC section of the product datasheet.
In both fixed and variable mode the Direct Memory Access Controller (DMAC) can be used to
reduce processor overhead.
The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the DMAC
is an optimal means, as the size of the data transfer between the memory and the SPI is either 8
bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be
reprogrammed.
The Variable Peripheral Selection allows buffer transfers with multiple peripherals without repro-
gramming the Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data
to be transmitted and the peripheral it is destined to. Using the DMAC in this mode requires 32-
bit wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in the MSBs, how-
ever the SPI still controls the number of bits (8 to16) to be transferred through MISO and MOSI
lines with the chip select configuration registers. This is not the optimal means in term of mem-
ory size for the buffers, but it provides a very effective means to exchange data with several
peripherals without any intervention of the processor.
• 8-bit Data:
• 8-bit to 16-bit Data:
Byte transfer,
PDC Pointer Address = Address + 1 byte,
PDC Counter = Counter - 1
2 bytes transfer. n-bit data transfer with don’t care data (MSB) filled with 0’s,
PDC Pointer Address = Address + 2 bytes,
PDC Counter = Counter - 1
6438F–ATARM–21-Jun-10