AT89LP6440-20JU Atmel, AT89LP6440-20JU Datasheet
AT89LP6440-20JU
Specifications of AT89LP6440-20JU
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AT89LP6440-20JU Summary of contents
Page 1
... Quasi-bidirectional (80C51 Style) • Input-Only (Tristate) • Push-pull CMOS Output • Open-drain Operating Conditions – 2.4V to 3.6V V Voltage Range DD – -40° 85°C Temperature Range – MHz @ 2.4–3.6V ® 51 Products 8-bit Microcontroller with 64K Bytes In-System Programmable Flash AT89LP6440 - Preliminary 3706A–MICRO–9/09 ...
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... Pin Configurations 1.1 40P6: 40-lead PDIP 1.2 44A: 44-lead TQFP (Top View) MOSI/P1.5 MISO/P1.6 SCK/P1.7 RST/P4.2 RXD/P3.0 TXD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 AT89LP6440 - Preliminary 2 T2/P1 VDD T2EX/P1 P0.0/AD0 SDA/P1 P0.1/AD1 SCL/P1 P0.2/AD2 SS/P1 P0.3/AD3 MOSI/P1 P0.4/AD4 MISO/P1 P0.5/AD5 SCK/P1 P0.6/AD6 RST/P4.2 ...
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... TXD/P3.1 13 INT0/P3.2 14 INT1/P3.3 15 T0/P3.4 16 T1/P3.5 17 MOSI/P1.5 1 MISO/P1.6 2 SCK/P1.7 3 RST/P4.2 4 RXD/P3.0 5 VDD 6 TXD/P3.1 7 INT0/P3.2 8 INT1/P3.3 9 T0/P3.4 10 T1/P3.5 11 NOTE: Bottom pad should be soldered to ground AT89LP6440 - Preliminary 39 P0.4/AD4 38 P0.5/AD5 37 P0.6/AD6 36 P0.7/AD7 35 P4.3 34 GND 33 P4.4/ALE 32 P4.5 31 P2.7/AIN3/A15 30 P2.6/AIN2/A14 29 P2.5/AIN1/A13 33 P0.4/AD4 32 P0.5/AD5 31 P0.6/AD6 30 P0.7/AD7 29 P4.3 28 GND 27 P4 ...
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... N/A 16 AT89LP6440 - Preliminary 4 Symbol Type Description I/O P1.5: User-configurable I/O Port 1 bit 5. I/O MOSI: SPI master-out/slave-in. When configured as master, this pin is an output. P1.5 When configured as slave, this pin is an input. I GPI5: General-purpose Interrupt input 5. I/O P1.6: User-configurable I/O Port 1 bit 6. ...
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... ADC5: ADC analog input 5. I/O P0.4: User-configurable I/O Port 0 bit 4. P0.4 O AD4: External memory interface Address/Data bit 4. I ADC4: ADC analog input 4. I/O P0.3: User-configurable I/O Port 0 bit 3. P0.3 O AD3: External memory interface Address/Data bit 3. I ADC3: ADC analog input 3. AT89LP6440 - Preliminary 5 ...
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... CPU core that can fetch a single byte from memory every clock cycle. In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instructions to execute in 12 clock cycles. In the AT89LP6440 CPU, standard instructions need only clock cycles providing times more throughput than the standard 8051. Seventy percent of instructions need only as many clock cycles as they have bytes to execute, and most of the remaining instructions require only one additional clock ...
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... Timer 0 and Timer 1 in the AT89LP6440 are enhanced with two new modes. Mode 0 can be configured as a variable 9- to 16-bit timer/counter and Mode 1 can be configured as a 16-bit auto-reload timer/counter. In addition, the timer/counters may each independently drive an 8-bit precision pulse width modulation output. ...
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... Comparison to Standard 8051 The AT89LP6440 is part of a family of devices with enhanced features that are fully binary com- patible with the 8051 instruction set. In addition, most SFR addresses, bit assignments, and pin alternate functions are identical to Atmel's existing standard 8051 products. However, due to the high performance nature of the device, some system behaviors are different from those of Atmel's standard 8051 products such as AT89S52 or AT89C2051 ...
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... I/O Ports The I/O ports of the AT89LP6440 may be configured in four different modes. By default all the I/O ports revert to input-only (tristated) mode at power-up or reset. In the standard 8051, all ports are weakly pulled high during power-up or reset. To enable 8051-like ports, the ports must be put into quasi-bidirectional mode by clearing the P1M0, P2M0, P3M0 and P4M0 SFRs ...
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... SIG In addition to the 64K code space, the AT89LP6440 also supports a 256-byte User Signature Array and a 128-byte Atmel Signature Array that are accessible by the CPU. The Atmel Signa- ture Array is initialized with the Device ID in the factory. The second page of the User Signature Array (0180H– ...
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... Internal Data Memory The AT89LP6440 contains 256 bytes of general SRAM data memory plus 128 bytes of I/O memory mapped into a single 8-bit address space. Access to the internal data memory does not require any configuration. The internal data memory has three address spaces: DATA, IDATA and SFR ...
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... The external memory space is accessed with the MOVX instructions. Some internal data memory resources are mapped into portions of the external address space as shown in the CPU can access them. The AT89LP6440 includes 4K bytes of on-chip Extra RAM (EDATA) and 8K bytes of nonvolatile Flash data memory (FDATA). Figure 3-3. ...
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... The FDATA address space accesses an internal nonvolatile data memory. This address space can be read just like EDATA by issuing a MOVX A,@DPTR; however, writes to FDATA require a more complex protocol and take several milliseconds to complete. The AT89LP6440 uses an idle-while-write architecture where the CPU is placed in an idle state while the write occurs. ...
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... Avoiding unnecessary page erases greatly improves the endurance of the memory. The AT89LP6440 includes 64 data pages of 128 bytes each. One or more bytes in a page may be written at one time. The AT89LP6440 includes a temporary page buffer of 64 bytes, or half of a page ...
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... For more details on using the Flash Data Memory, see the application note titled “AT89LP Flash Data Memory”. FDATA may also be programmed by an external device programmer (See tion 25. on page 3706A–MICRO–9/09 AT89LP6440 - Preliminary FDATA Page Write DMEN MWEN LDPG ...
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... External Memory Interface The AT89LP6440 uses the standard 8051 external memory interface with the upper address on Port 2, the lower address and data in/out multiplexed on Port 0, and the ALE, RD and WR strobes. The interface may be used in two different configurations depending on which type of MOVX instruction is used to access XDATA ...
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... ALE – XSTK 5 4 Wait States Strobe Width CYC CYC CYC CYC AT89LP6440 - Preliminary EXTERNAL DATA MEMORY DATA LATCH ADDR I/O PAGE WE OE BITS Reset Value = xxx0 0000B WS1 WS0 EXRAM Section 10.1 “Port Configuration” on page ALES 0 44. Port 0 17 ...
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... Figure 3-9. CLK ALE Figure 3-10. External Data Memory Read Cycle (WS = 00B) CLK ALE AT89LP6440 - Preliminary 18 and Figure 3-10 show examples of external data memory write and read cycles, Section 6.5 on page External Data Memory Write Cycle (WS = 00B) ...
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... P0 3.4 Extended Stack The AT89LP6440 provides an extended stack space for applications requiring additional stack memory. By default the stack is located in the 256-byte IDATA space of internal data memory. The IDATA stack is referenced solely by the 8-bit Stack Pointer (SP: 81H). Setting the XSTK bit in AUXR enables the extended stack. The extended stack resides in the EDATA space for up to 4KB of stack memory ...
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... In-Application Programming (IAP) The AT89LP6440 supports In-Application Programming (IAP), allowing the program memory to be modified during execution. IAP can be used to modify the user application on the fly or to use program memory for nonvolatile data storage. The same page structure write protocol for FDATA also applies to IAP (See always placed in idle while modifying the program memory ...
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... Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write to these unlisted locations, since they may be used in future products to invoke new features. Table 4-1. AT89LP6440 SFR Map and Reset Values 8 9 0F8H ...
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... Enhanced CPU The AT89LP6440 uses an enhanced 8051 CPU that runs times the speed of standard 8051 devices ( times the speed of X2 8051 devices). The increase in performance is due to two factors. First, the CPU fetches one instruction byte from the code memory every clock cycle ...
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... Multiply–Accumulate Unit (MAC) The AT89LP6440 includes a multiply and accumulate (MAC) unit that can significantly speed up many mathematical operations required for digital signal processing. The MAC unit includes a 16-by-16 bit multiplier and a 40-bit adder that can perform integer or fractional multiply-accumu- late operations on signed 16-bit input values ...
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... Enhanced Dual Data Pointers The AT89LP6440 provides two 16-bit data pointers: DPTR0 formed by the register pair DPOL and DPOH (82H an 83H), and DPTR1 formed by the register pair DP1L and DP1H (84H and 85H). The data pointers are used by several instructions to access the program or data memo- ries ...
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... MOVC instructions. • In some cases, both data pointers must be used simultaneously. To prevent frequent toggling of DPS, the AT89LP6440 supports a prefix notation for selecting the opposite data pointer per instruction. All DPTR instructions, with the exception of JMP @A+DPTR, when prefixed with an 0A5H opcode will use the inverse value of DPS (DPS) to select the data pointer ...
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... Data Pointer Update The Dual Data Pointers on the AT89LP6440 include two features that control how the data pointers are updated. The data pointer decrement bits, DPD1 and DPD0 in DPCF, configure the INC DPTR instruction to act as DEC DPTR. The resulting operation will depend on DPS as shown in Table 5-3 ...
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... DPTR0 and /DPTR will target DPTR1. When DPS = 1, DPTR will target DPTR1 and /DPTR will target DPTR0. 5.2.2 Data Pointer Operating Modes The Dual Data Pointers on the AT89LP6440 include three additional operating modes that affect data pointer based instructions. These modes are controlled by bits in DSPR. 5.2.2.1 DPTR Redirect The Data Pointer Redirect to B bit, DPRB (DSPR ...
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... Circular Buffers The CBE0 and CBE1 bits in DSPR can configure DPTR0 and DPTR1, respectively, to operate in circular buffer mode. The AT89LP6440 maps circular buffers into two identically sized regions of EDATA/XDATA. These buffers can speed up convolution computations such as FIR and IAR digital filters. The length of the buffers are set by the value of the FIRD (E3H) register for up to 256 entries ...
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... The JMP @A+PC instruction supports localized jump tables without using a data pointer. • The CJNE A, @R • The BREAK instruction is used by the On-Chip Debug system. See 3706A–MICRO–9/09 lists the additions to the 8051 instruction set that are supported by the AT89LP6440. 147. AT89LP6440 Extended Instructions Mnemonic ...
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... When using the crystal oscillator, P4.0 and P4.1 will have their inputs and outputs disabled. Also, XTAL2 in crystal oscillator mode should not be used to directly drive a board-level clock without a buffer. Figure 6-1. Note: AT89LP6440 - Preliminary 30 164. By default, no internal clock division is used to generate the CPU clock “Reset” on page 32 or “ ...
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... System Clock Out When the AT89LP6440 is configured to use either an external clock or the internal RC oscillator, the system clock divided by 2 may be output on XTAL2 (P4.1). The clock out feature is enabled by setting the COE bit in CLKREG. For example, setting COE = “1” when using the internal oscil- lator will result in a 4.0 MHz (± ...
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... During reset, all I/O Registers are set to their initial values, the port pins are tristated, and the program starts execution from the Reset Vector, 0000H. The AT89LP6440 has five sources of reset: power-on reset, brown-out reset, external reset, watchdog reset, and software reset. ...
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... POR DD t SUT t POR RST RST (RST Controlled Externally approximately 143 µs ± 5%. POR (Table 7-1). The Start-Up Time fuses also control the length of the start-up time AT89LP6440 - Preliminary V POR (RST Tied RHD as shown in Figure 7-2. However, if this event BOD (RST Tied to V ...
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... SUT Fuse 1 7.2 Brown-out Reset The AT89LP6440 has an on-chip Brown-out Detection (BOD) circuit for monitoring the V during operation by comparing fixed trigger level. The trigger level V nominally 2.0V. The purpose of the BOD is to ensure that if V speed, the system will gracefully enter reset without the possibility of errors induced by incorrect execution ...
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... WDTOVF and SWRST to flag an error. 8. Power Saving Modes The AT89LP6440 supports two different power-reducing modes: Idle and Power-down. These modes are accessed through the PCON register. Additional steps may be required to achieve the lowest possible power consumption while using these modes. ...
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... After the time-out period the interrupt service routine will begin. The time-out period is controlled by the Start-up Timer Fuses (see The interrupt pin need not remain low for the entire time-out period. AT89LP6440 - Preliminary 36 PWDEX ...
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... If the Brown-out Detector is not needed by the application, this module should be turned off. If the Brown-out Detector is enabled by the BOD Enable Fuse, it will be enabled in all modes except Power-down. See 3706A–MICRO–9/09 AT89LP6440 - Preliminary Interrupt Recovery from Power-down (PWDEX = 0) t SUT Interrupt Recovery from Power-down (PWDEX = 1) ...
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... IRC is the system clock source) and when the internal reference is disabled (IREF = 0). The DADC must always be disabled before entering power-down. 9. Interrupts The AT89LP6440 provides 12 interrupt sources: two external interrupts, three timer interrupts, a serial port interrupt, an analog comparator interrupt, a general-purpose interrupt, a com- pare/capture interrupt, a two-wire interrupt, an ADC interrupt and an SPI interrupt. These interrupts and the system reset each have a separate program vector at the start of the program memory space ...
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... TWSR and respond accordingly before the bit is cleared by software. All of the bits that generate interrupts can be set or cleared by software, with the same result as though they had been set or cleared by hardware. That is, interrupts can be generated and pending interrupts can be canceled in software. 3706A–MICRO–9/09 AT89LP6440 - Preliminary 39 ...
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... If the instruction in progress is RETI with XSTK, the additional wait time cannot be more than 14 cycles (a maximum of 5 more cycles to complete the instruction in progress, plus a maximum of 9 cycles to complete the next instruction). Thus single-inter- AT89LP6440 - Preliminary 40 Interrupt Vector Addresses ...
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... External Interrupt 1 Enable ET0 Timer 0 Interrupt Enable EX0 External Interrupt 0 Enable . 3706A–MICRO–9/09 and Figure 9-2. 5 LCALL 1st ISR Instr. 6 RETI MAC AB ET2 AT89LP6440 - Preliminary 15 21 Ack. LCALL Reset Value = 0000 0000B ET1 EX1 ET0 1st ISR Instr. EX0 0 41 ...
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... Symbol Function IP2D Interrupt Priority 2 Disable. Set IP2D disable all interrupts with priority level two. Clear enable all interrupts with priority level two when PTWI Two-wire Interface Interrupt Priority Low PADC ADC Interrupt Priority Low AT89LP6440 - Preliminary 42 – ETWI EADC PT2 ...
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... PTWH Two-Wire Interface Interrupt Priority High PADH ADC Interrupt Priority High PSPH Serial Peripheral Interface Interrupt Priority High PCCH Compare/Capture Array Interrupt Priority High PGPH General-purpose Interrupt 0 Priority High 3706A–MICRO–9/09 AT89LP6440 - Preliminary PT2H PSH PT1H – PTWH PADH 5 4 ...
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... I/O Ports The AT89LP6440 can be configured for between 35 and 38 I/O pins. The exact number of I/O pins available depends on the clock and reset options as shown in Table 10-1. Clock Source External Crystal or Resonator External Clock Internal RC Oscillator 10.1 Port Configuration All port pins on the AT89LP6440 may be configured to one of four modes: quasi-bidirectional (standard 8051 port outputs), push-pull output, open-drain output, or input-only ...
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... P3.2, P3.3, P4.2, P4.0 and P4.1 is not disabled during Power-down (see fore these pins should not be left floating during Power-down when configured in this mode. Figure 10-2. Input Only 3706A–MICRO–9/09 1 Clock Delay (D Flip-Flop) From Port Register Input Data PWD AT89LP6440 - Preliminary Figure 10- Very Strong ...
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... The push-pull mode may be used when more source current is needed from a port output. The push-pull port configuration is shown in Figure 10-5. Push-pull Output From Port Register AT89LP6440 - Preliminary 46 Input Data Figure 10-4. The input circuitry of P3.2, P3.3, P4.0, P4.1 and P4.2 is not ...
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... Port Analog Functions The AT89LP6440 incorporates two analog comparators and an 8-channel analog-to-digital con- verter. In order to give the best analog performance and minimize power consumption, pins that are being used for analog functions must have both their digital outputs and digital inputs dis- abled ...
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... Port Alternate Functions Most general-purpose digital I/O pins of the AT89LP6440 share functionality with the various I/Os needed for the peripheral units. Alternate functions are connected to the pins in a logic AND fashion. In order to enable the alternate function on a port pin, that pin must have a “1” in its corresponding port register bit, otherwise the input/output will always be “ ...
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... P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.2 P4.6 P4.7 3706A–MICRO–9/09 AT89LP6440 - Preliminary Port Pin Alternate Functions Configuration Bits PxM0.y PxM1.y P1M0.2 P1M1.2 P1M0.3 P1M1.3 P1M0.4 P1M1.4 P1M0.5 P1M1.5 P1M0.6 P1M1.6 P1M0.7 P1M1.7 P2M0 ...
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... Enhanced Timer 0 and Timer 1 with PWM The AT89LP6440 has two 16-bit Timer/Counters, Timer 0 and Timer 1, with the following features: • Two 16-bit timer/counters with 16-bit reload registers • Two independent 8-bit precision PWM outputs with 8-bit prescalers • UART or SPI baud rate generation using Timer 1 • ...
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... Mode 0 operation as it applies to Timer 1 in 13-bit mode. As the count Mode 0: Time-out Period RH1/RL1 are not required by Timer 1 during Mode 0 and may be used as temporary storage registers. OSC ÷TPS C C Pin Control TR1 GATE1 Figure Mode 1: Time-out Period AT89LP6440 - Preliminary PSC0 + 1 × 256 2 × ( ------------------------------------------------------ - = TPS + Oscillator Frequency TL1 (8 Bits) ...
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... TR1 and TF1 from Timer 1. Thus, TH0 now controls the Timer 1 interrupt. While Timer Mode 3, Timer 1 will still obey its settings in TMOD but cannot generate an interrupt. AT89LP6440 - Preliminary 52 ÷TPS ...
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... Mode 3 is for applications requiring an extra 8-bit timer or counter. With Timer 0 in Mode 3, the AT89LP6440 can appear to have four Timer/Counters. When Timer Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3. In this case, Timer 1 can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt ...
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... AT89LP6440 - Preliminary 54 T1M1 T1M0 GATE0 Operation Variable 9–16-bit Timer Mode. 8-bit Timer/Counter TH1 with TL1 as 1–8-bit prescaler. 16-bit Auto-Reload Mode. TH1 and TL1 are cascaded to form a 16-bit Timer/Counter that is reloaded with RH1 and RL1 each time it overflows. 8-bit Auto Reload Mode. TH1 holds a value which is reloaded into 8-bit Timer/Counter TL1 each time it overflows ...
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... PSC00 11.5 Pulse Width Modulation On the AT89LP6440, Timer 0 and Timer 1 may be independently configured as 8-bit asymmetri- cal (edge-aligned) pulse width modulators (PWM) by setting the PWM0EN or PWM1EN bits in TCONB, respectively. In PWM Mode the generated waveform is output on the timer's input pin T1. Therefore, C/Tx must be set to “0” when in PWM mode and the T0 (P3.4) and T1 (P3 ...
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... T0 is toggled at every TL0 overflow (see Figure 11-9 on page used to output a square wave of varying frequency. THx acts as an 8-bit counter. The following formula gives the output frequency for Timer 0 in PWM Mode 2. AT89LP6440 - Preliminary 56 Oscillator Frequency ------------------------------------------------------ - ...
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... OSC Control TR1 GATE1 INT1 Pin {RH0 & RL0}/{RH1 & RL1} are not required by Timer 0/Timer 1 during PWM Mode 2 and may be used as temporary storage registers. FFh THx Tx AT89LP6440 - Preliminary RH1 (8 Bits) RL1 OCR1 (8 Bits) = TL1 TH1 (8 Bits) (8 Bits) TH1 ...
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... TH0. PWM Mode 3 is for applications requiring a single PWM channel and two timers, or two PWM channels and an extra timer or counter. With Timer 0 in PWM Mode 3, the AT89LP6440 can appear to have four Timer/Counters. When Timer PWM Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3 ...
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... Enhanced Timer 2 The AT89LP6440 includes a 16-bit Timer/Counter 2 with the following features: • 16-bit timer/counter with one 16-bit reload/capture register • One external reload/capture input • Up/Down counting mode with external direction control • UART baud rate generation • Output-pin toggle on timer overflow • ...
Page 60
... PHSD also determines the initial phase relationship for 2 phase modes. PHSD Direction → → → → → → AT89LP6440 - Preliminary 60 Table 12-4). The register pair {TH2, TL2} at addresses 0CDH and 0CCH are the RCLK TCLK EXEN2 PHS1 PHS0 T2CM1 ...
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... Count Mode Standard Timer 2 (up count: BOTTOM Clear on RCAP compare (up count: MIN Dual-slope with single update (up-down count: Dual-slope with double update (up-down count: Capture Mode: Time-out Period AT89LP6440 - Preliminary → MAX ) → TOP ) → → MIN TOP MIN ) → ...
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... T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt. The Timer 2 overflow rate for this mode is given in the following equation: Auto-Reload Mode: DCEN = 0, T2CM = 00B Timer 2 may also be configured to count from MIN to TOP instead of BOTTOM to MAX by set- ting T2CM AT89LP6440 - Preliminary 62 C/ TL2 TR2 C/ CAPTURE ...
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... BOTTOM, the 16-bit value in RCAP2H and RCAP2L reloaded into the timer 3706A–MICRO–9/09 Time-out Period Figure 12-3. T2CM = 00B, DCEN = 0 1-0 T2CM = 01B, DCEN = 0 1-0 = 00B, the timer will overflow at MAX and set the TF2 bit. This overflow 1-0 AT89LP6440 - Preliminary { RCAP2H RCAP2L , } + 1 ----------------------------------------------------------------- - = Oscillator Frequency TL2 TH2 TF2 Set ...
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... Changes to the count direction may result in longer or shorter periods between time-outs. Figure 12-5. Timer 2 Diagram: Auto-Reload Mode (T2CM ÷TPS AT89LP6440 - Preliminary 64 = 01B, the timer will overflow at TOP and set the TF2 bit. This 1-0 Figure 12-6 ...
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... DCEN = 0, T2CM = 10B 3706A–MICRO–9/09 T2CM = 00B, DCEN = 1 1-0 T2CM = 01B, DCEN = 1 1-0 = 11B), the timer operates in a dual slope fashion. The timer counts up from MIN to 1-0 Time-out Period AT89LP6440 - Preliminary TF2 Set TF2 Set = 10B) or Count Mode 3 1-0 × RCAP2H RCAP2L × ...
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... TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an inter- rupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer use as a baud rate gen- AT89LP6440 - Preliminary 66 MAX ...
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... RCAP2H and RCAP2L. 3706A–MICRO–9/09 C/ TL2 TR2 C/ RCAP2L EXF2 EXEN2 T2CM = 00B Clock Out Frequency T2CM = 01B Clock Out Frequency AT89LP6440 - Preliminary TIMER 1 OVERFLOW ÷ 2 "0" "1" SMOD1 "1" "0" TH2 RCLK ÷ 16 "1" ...
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... T2 PIN T2EX PIN 13. Compare/Capture Array The AT89LP6440 includes a four channel Compare/Capture Array (CCA) that performs a variety of timing operations including input event capture, output compare waveform generation and pulse width modulation (PWM). Timer 2 serves as the time base for the four 16-bit compare/cap- ture modules. The CCA has the following features: • ...
Page 69
... The configuration bits for each channel are stored in the CCCx registers accessible through T2CCC. See 3706A–MICRO–9/09 ÷TPS C/ C/T2 =1 TR2 CCCA CCCB CCCC CCCD T2CCA T2CCC Table 13-5 on page 73 for a description of the CCCx register. AT89LP6440 - Preliminary RCAP2L RCAP2H TL2 TH2 TF2 T2CCF CCAL CCAH CCBL CCBH CCCL CCCH CCDL CCDH ...
Page 70
... T2CCA. Writes to T2CCL will update the selected CCA channel with the 16-bit contents of T2CCH and T2CCL. Note: All writes/reads to/from T2CCL will access channel X as currently selected by T2CCA.The data registers for the remaining unselected channels are not accessible. AT89LP6440 - Preliminary 70 — — ...
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... Figure 13-2. CCA Capture Mode Diagram (P2.x) CCx Each CCA channel has an associated external capture input pin: CCA (P2.0), CCB (P2.1), CCC (P2.2) and CCD (P2.3). External capture events are always edge-triggered and can be selected 3706A–MICRO–9/09 AT89LP6440 - Preliminary – – CCFD 5 ...
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... Down = 1) at the time of the event will be captured into the channel’s CDIRx bit in CCCx. CTCx must be cleared to 0 for all channels if Timer 2 is operating in Baud Rate mode or errors may occur in the serial communication. AT89LP6440 - Preliminary 72 = 1xB), the count 1-0 3706A– ...
Page 73
... Toggle CCx pin on compare match 0 Inverting Pulse Width Modulation 1 Non-Inverting Pulse Width Modulation 0 Reserved 1 Reserved bits in ACSRA. See 2-0 bits in ACSRB. See 2-0 AT89LP6440 - Preliminary Reset Value = 00X0 0000B CxM2 CxM1 CxM0 2 1 (2) (3) (4) (4) Table 19-1 on page 130. Table 19-2 on page 131 ...
Page 74
... A wide range of waveform generation configurations are possible using the various operating modes of Timer 2 and the CCA. Some example configurations are detailed below. Pulse width modulation is a special case of output compare. See PWM operation. AT89LP6440 - Preliminary 74 00H 00H TL2 ...
Page 75
... TOP value and the compare values more frequently. 3706A–MICRO–9/09 CP/RL2 = 0, T2CM {CCAH,CCAL} {CCBH,CCBL} CCA CCB {CCAH,CCAL} CCA AT89LP6440 - Preliminary Figure 13-4 shows an example of outputting = 01B, DCEN = 0 1-0 Figure 13-5 shows an example wave- CP/RL2 = 1 = 1xB. In this mode the frequency 1-0 ...
Page 76
... TOP value of the timer. The CCA PWM always uses the greatest precision allowable for the selected output frequency, as compared to Timer 0 and 1 whose PWMs are fixed at 8-bit precision regardless of frequency. Figure 13-7. CCA PWM Mode Diagram AT89LP6440 - Preliminary 76 CP/RL2 = 0, T2CM {CCAH,CCAL} ...
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... OUT { RCAP2H RCAP2L Inverting: Duty Cycle Non-Inverting: Duty Cycle = 100% CP/RL2 = 0, T2CM {CCxH,CCxL} Inverted CCx Non-inverted Figure 13-9. The timer counts up from MIN to TOP and then counts down from TOP to AT89LP6440 - Preliminary 1 × -------------------- - , } + 1 TPS + 1 { CCxH CCxL , } × --------------------------------------------------------------- - 100% = RCAP2H RCAP2L ...
Page 78
... MIN (underflow) and TOP (over- flow). The resulting waveform may not be completely symmetrical around the TOP value as shown in However, this allows the pulses to be weighted toward one edge or another. The TF2 interrupt flag is set at both underflow and overflow. AT89LP6440 - Preliminary 78 Oscillator Frequency ---------------------------------------------------------------- - f = × ...
Page 79
... Multi-Phasic PWM The PWM channels may be configured to provide multi-phasic alternating outputs by the PHS bits in T2MOD. The AT89LP6440 provides 1 out out out of 4 and 2 out of 4 phase modes (See are connected to a one-hot shift register that selectively enables and disables the outputs (See Figure the compare value was set equal to TOP ...
Page 80
... CCB 0 EN CCC 1 EN CCD 1 EN Figure 13-13. Three-Phase Mode with Channel B Disabled CCA CCB CCC PHSD AT89LP6440 - Preliminary 80 Summary of Multi-Phasic Modes Mode PHSD = 0 Off Normal Operation (all channels active at all times) → → → 1 → → → → → 1:3 ...
Page 81
... CCC CCD 14. External Interrupts The INT0 (P3.2) and INT1 (P3.3) pins of the AT89LP6440 may be used as external interrupt sources. The external interrupts can be programmed to be level-activated or transition-activated by setting or clearing bit IT1 or IT0 in Register TCON. If ITx = 0, external interrupt x is triggered by a detected low at the INTx pin. If ITx = 1, external interrupt x is edge-triggered. In this mode if successive samples of the INTx pin show a high in one cycle and a low in the next cycle, inter- rupt request flag IEx in TCON is set ...
Page 82
... GPIF register is set. The flags in GPIF must be cleared by software. Any GPI interrupt may wake up the device from the Power-down state. Figure 15-1. GPI Block Diagram (P1.7) GPI7 (P1.6) GPI6 (P1.5) GPI5 (P1.4) GPI4 (P1.3) GPI3 (P1.2) GPI2 (P1.1) GPI1 (P1.0) GPI0 AT89LP6440 - Preliminary 82 GPLS GPMOD GPIEN ...
Page 83
... Table 15-4. – General-purpose Interrupt Flag Register GPIF GPIF = 9DH Not Bit Addressable GPIF7 GPIF6 Bit 7 6 GPIF interrupt on P1.x inactive 1 = interrupt on P1.x active. Must be cleared by software. 3706A–MICRO–9/09 AT89LP6440 - Preliminary GPMOD5 GPMOD4 GPMOD3 GPLS5 GPLS4 GPLS3 GPIEN5 GPIEN4 GPIEN3 ...
Page 84
... Serial Interface (UART) The serial interface on the AT89LP6440 implements a Universal Asynchronous Receiver/Trans- mitter (UART). The UART has the following features: • Full-duplex Operation • Data Bits • Framing Error Detection • Multiprocessor Communication Mode with Automatic Address Recognition • Baud Rate Generator Using Timer 1 or Timer 2 • ...
Page 85
... REN TB8 5 4 SM1 Mode Description 0 0 shift register 1 1 8-bit UART 0 2 9-bit UART 1 3 9-bit UART AT89LP6440 - Preliminary See “Automatic Address Recognition” on page 96. Reset Value = 0000 0000B RB8 (2) Baud Rate Timer 1 osc osc variable (Timer 1 or Timer /16 ...
Page 86
... Programmers can achieve very low baud rates with Timer 1 by configuring the Timer to run as a 16-bit auto-reload timer (high nibble of TMOD = 0001B). In this case, the baud rate is given by the following formula. Table 16-2 AT89LP6440 - Preliminary 86 SMOD1 Mode 0 Baud Rate 2 ...
Page 87
... Timer 2. Commonly Used Baud Rates Generated by Timer 2 (TPS = 0000B) f (MHz) CP/RL2 OSC 12 11.059 9.6K 11.059 4.8K 11.059 2.4K 11.059 1.2K 11.059 137.5 11.986 110 6 110 12 AT89LP6440 - Preliminary Timer 1 SMOD1 C/T Mode ...
Page 88
... SMOD1 bits as listed in idle state of the clock when not currently transmitting/receiving. The SMOD1 bit determines if the output data is stable for both edges of the clock, or just one. Table 16-5. SM2 AT89LP6440 - Preliminary 88 Figure 16-1 on page 89 Table 16-4 Mode 0 Baud Rates SMOD1 Baud Rate 0 f ...
Page 89
... TIMER 1 OVERFLOW f osc 1 0 TB8 ÷2 ÷ SMOD1 WRITE TO SBUF SEND SHIFT RXD (DATA OUT) TXD (SHIFT CLOCK) TI WRITE TO SCON (CLEAR RI) RI RECEIVE SHIFT RXD (DATA IN) TXD (SHIFT CLOCK) 3706A–MICRO–9/09 AT89LP6440 - Preliminary INTERNAL BUS “1“ INTERNAL BUS SM2 89 ...
Page 90
... RXD SM2 P3.0 Write to SBUF TI Mode 0 transfers data LSB first whereas SPI or TWI are generally MSB first. Emulation of these interfaces may require bit reversal of the transferred data bytes. The following code example reverses the bits in the accumulator: EX: REVRS: RLC AT89LP6440 - Preliminary ...
Page 91
... On receive, the stop bit goes into RB8 in SCON. In the AT89LP6440, the baud rate is determined either by the Timer 1 overflow rate, the TImer 2 over- flow rate, or both. In this case one timer is for transmit and the other is for receive. ...
Page 92
... DETECTOR RXD TX CLOCK WRITE TO SBUF SEND DATA SHIFT D0 TXD START BIT TI ÷16 RESET RX CLOCK RXD START BIT BIT DETECTOR SAMPLE TIMES SHIFT RI AT89LP6440 - Preliminary 92 INTERNAL BUS “1” SBUF CL ZERO DETECTOR SHIFT DATA START TX CONTROL ÷16 RX CLOCK SEND TI TI SERIAL PORT ÷ ...
Page 93
... RXD input. Note that the value of the received stop bit is irrelevant to SBUF, RB8, or RI. 3706A–MICRO–9/09 AT89LP6440 - Preliminary show a functional diagram of the serial port in Modes 2 and 3. The and Either SM2 = 0 or the received 9th data bit = 1 ...
Page 94
... Figure 16-5. Serial Port Mode 2 CPU CLOCK SMOD1 1 SMOD1 0 AT89LP6440 - Preliminary 94 INTERNAL BUS INTERNAL BUS 3706A–MICRO–9/09 ...
Page 95
... SHIFT DATA START TX CONTROL ÷16 RX CLOCK SEND TI SERIAL PORT ÷16 LOAD RX CLOCK RI SBUF START RX CONTROL SHIFT 1FFH BIT DETECTOR INPUT SHIFT REG. (9 BITS) LOAD SBUF SBUF READ SBUF INTERNAL BUS AT89LP6440 - Preliminary TXD SHIFT D6 D7 TB8 STOP BIT RB8 STOP BIT 95 ...
Page 96
... A unique address for slave 1 would be 1100 0001 since a “1” in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit (for slave 0) and bit (for slave 1). Thus, both could be addressed with 1100 0000. AT89LP6440 - Preliminary 96 SADDR = 1100 0000 ...
Page 97
... Enhanced Serial Peripheral Interface The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT89LP6440 and peripheral devices or between multiple AT89LP6440 devices, including multi- ple masters and slaves on a single bus. The SPI includes the following features: • Full-duplex, 3-wire or 4-wire Synchronous Data Transfer • ...
Page 98
... Shift Register.The slave may ignore SS by setting its SSIG bit in SPSR. When SSIG = 1, the slave is always enabled and operates in 3-wire mode. However, the slave output on MISO may still be disabled by setting DISSO = 1. AT89LP6440 - Preliminary 98 Oscillator MSB ...
Page 99
... Master Operation An SPI master device initiates all data transfers on the SPI bus. The AT89LP6440 is configured for master operation by setting MSTR = 1 in SPCR. Writing to the SPI data register (SPDR) while in master mode loads the transmit buffer. If the SPI shift register is empty, the byte in the transmit buffer is moved to the shift register ...
Page 100
... Slave Operation When the AT89LP6440 is not configured for master operation, MSTR = 0, it will operate as an SPI slave. In slave mode, bytes are shifted in through MOSI and out through MISO by a master device controlling the serial clock on SCK. When a byte has been transferred, the SPIF flag is set to “ ...
Page 101
... In Push-Pull mode MOSI is active only during transfers, otherwise it is tristated to prevent line contention. A weak external pull-up may be required to prevent MOSI from floating. DORD MSTR CPOL AT89LP6440 - Preliminary Slave (MSTR = 0) Input (Internal Pull-up) Input (Tristate) Input (Tristate) Input (External Pull-up) Input (Internal Pull-up) Input (Tristate) ...
Page 102
... ESP = 1. MODF must be cleared by software. Transmit Buffer Empty Flag. Set by hardware when the transmit buffer is loaded into the shift register, allowing a new byte TXE to be loaded. TXE must be cleared by software. When ENH = 1 and ESP = 1, TXE will generate an interrupt. AT89LP6440 - Preliminary 102 SCK (TSCK = 1) f ...
Page 103
... SCK (CPOL = 0) SCK (CPOL = 1) MOSI (FROM MASTER) MISO (FROM SLAVE) SS (TO SLAVE) Note: *Not defined but normally LSB of previously transmitted character. 3706A–MICRO–9/09 Figures 17-3 and 17-4. To prevent glitches on SCK from disrupting the MSB MSB AT89LP6440 - Preliminary LSB LSB 103 ...
Page 104
... Note that all AT89LP devices connected to the TWI bus must be powered in order to allow any bus operation. The number of devices that can be connected to the bus is only limited by the bus capacitance limit of 400 pF and the 7-bit slave address space. AT89LP6440 - Preliminary 104 Figure 18-1 ...
Page 105
... SDA low in the ninth SCL (ACK) cycle. If the addressed Slave is busy, or for some other reason can not service the Mas- 3706A–MICRO–9/09 SDA SCL Data Stable Data Change START STOP START AT89LP6440 - Preliminary Data Stable REPEATED START STOP 105 ...
Page 106
... Transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first. Figure 18-5. Data Packet Format Aggregate SDA from Transmitter SDA from Receiver SCL from Master AT89LP6440 - Preliminary 106 Addr MSB 1 2 START Data MSB SDA 1 2 ...
Page 107
... SCL high and low Time-out periods when the combined SCL line goes high or low, respectively. 3706A–MICRO–9/09 shows a typical data transmission. Note that several data bytes can be transmitted Addr LSB R/W ACK Data MSB SLA+R/W AT89LP6440 - Preliminary Data LSB ACK Data Byte STOP 107 ...
Page 108
... SDA from SDA from Synchronized SCL Line Note that arbitration is not allowed between: • A REPEATED START condition and a data bit. • A STOP condition and a data bit. • A REPEATED START and a STOP condition. AT89LP6440 - Preliminary 108 TA low Line TB low Masters Start Counting Low Period ...
Page 109
... Bus Interface Unit START / STOP Spike Suppression Control Address/Data Shift Arbitration Detection Register (TWDR) Address Match Unit Address Register (TWAR) Address Comparator AT89LP6440 - Preliminary Figure 18-9. All registers Spike Filter Bit Rate Generator Prescaler Bit Rate Register Ack (TWBR) Control Unit ...
Page 110
... After the TWI has been addressed by own slave address or general call. • After the TWI has received a data byte. • After a STOP or REPEATED START has been received while still addressed as a Slave. • When a bus error has occurred due to an illegal START or STOP condition. AT89LP6440 - Preliminary 110 System Clock SCL frequency ...
Page 111
... General Call Enable. Set to enable General Call address (00h) recognition. Clear to disable General Call address GC recognition. 3706A–MICRO–9/09 STA STO TWIF TWS5 TWS4 TWS3 TWA4 TWA3 TWA2 AT89LP6440 - Preliminary Reset Value = X000 00XXB AA – Reset Value = 1111 1000B Table 18-6 through Reset Value = 1111 1110B TWA1 TWA0 2 1 – ...
Page 112
... TWI bus cycle by manipulating the TWCR and TWDR registers. Figure 18-10 this example, a Master wishes to transmit a single data byte to a Slave. This description is quite abstract, a more detailed explanation follows later in this section. A simple code example imple- menting the desired behavior is also presented. AT89LP6440 - Preliminary 112 TWD5 TWD4 TWD3 ...
Page 113
... TWCR, making sure that TWIF is written to zero. SLA TWIF set. Status code indicates SLA+W sent, ACK received AT89LP6440 - Preliminary 7. Check TWSR to see if data was sent and ACK received. Application loads appropriate control signals to send STOP into TWCR, making sure that TWIF is written to zero. Data A STOP 6 ...
Page 114
... These figures contain the following abbreviations: S: START condition Rs: REPEATED START condition R: Read bit (high level at SDA) W: Write bit (low level at SDA) A: Acknowledge bit (low level at SDA) A: Not acknowledge bit (high level at SDA) Data: 8-bit data byte P: STOP condition AT89LP6440 - Preliminary 114 3706A–MICRO–9/09 ...
Page 115
... TWIF flag is set. The num- Table 18-6 to Table 18-9. – TWEN STA STO Table 18-6). In order to enter MT mode, SLA+W must be transmitted. This is done by Table 18-6. – TWEN STA STO – TWEN STA STO AT89LP6440 - Preliminary TWIF AA – TWIF AA – TWIF AA – – X – X – X 115 ...
Page 116
... Data byte has been 28h transmitted; ACK has been received Data byte has been 30h transmitted; NOT ACK has been received Arbitration lost in SLA+W 38h or data bytes AT89LP6440 - Preliminary 116 Application Software Response To TWCR To/from TWDR STA STO TWIF Load SLA ...
Page 117
... In the Master Receiver mode, a number of data bytes are received from a slave transmitter. In order to enter a Master mode, a START condition must be transmitted. The format of the follow- ing address packet determines whether Master Transmitter or Master Receiver mode entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered. 3706A–MICRO–9/09 AT89LP6440 - Preliminary DATA 18h ...
Page 118
... ACK has been returned Data byte has been 58h received; NOT ACK has been returned AT89LP6440 - Preliminary 118 Table 18-7). In order to enter MR mode, SLA+R must be transmitted. Table 18-7. Received data can be read from the TWDR Register when the TWIF flag ...
Page 119
... This number (contained in TWSR) corresponds defined state of the Two-wire Serial Bus. The prescaler bits are zero or masked to zero TWA6 TWA5 TWA4 Device’s own Slave Address – TWEN STA AT89LP6440 - Preliminary A DATA A P 50h 58h R S 10h Other master A continues 38h ...
Page 120
... Arbitration lost in SLA+R/W as master; General call 78h address has been received; ACK has been returned Previously addressed with own SLA+W; data has been 80h received; ACK has been returned AT89LP6440 - Preliminary 120 Application Software Response To TWCR To/from TWDR STA STO TWIF No action X ...
Page 121
... No Action Action AT89LP6440 - Preliminary Switched to the not addressed Slave mode recognition of own SLA or GCA Switched to the not addressed Slave mode; 1 own SLA will be recognized; GCA will be recognized “1” Switched to the not addressed Slave mode; no recognition of own SLA or GCA; a START ...
Page 122
... Reception of the general call address and one or more data bytes Last data byte received is not acknowledged Arbitration lost as master and addressed as slave by general call From master to slave From slave to master AT89LP6440 - Preliminary 122 SLA W A DATA 60h A 68h General Call ...
Page 123
... From slave to master 3706A–MICRO–9/09 SLA R A DATA A8h A B0h DATA A n AT89LP6440 - Preliminary A DATA A B8h C0h A C8h Any number of data bytes and their associated acknowledge bits This number (contained in TWSR) corresponds to a defined state of the Two-wire Serial Bus. The ...
Page 124
... Data byte in TWDR has C0h been transmitted; NOT ACK has been received Last data byte in TWDR has C8h been transmitted (AA = “0”); ACK has been received AT89LP6440 - Preliminary 124 Application Software Response To TWCR To/from TWDR STA STO TWIF Load data byte ...
Page 125
... To TWCR To/from TWDR STA STO TWIF No action No action No action AT89LP6440 - Preliminary Table AA Next Action Taken by TWI Hardware Wait or proceed current transfer Only the internal hardware is affected, no STOP X condition is sent on the bus. In all cases, the bus is released and STO is cleared. 18-10. 125 ...
Page 126
... Figure 18-15. Combining Several TWI Modes to Access a Serial EEPROM START 19. Dual Analog Comparators The AT89LP6440 provides two analog comparators. The analog comparators have the following features: • Internal 3-level Voltage Reference (1.125V, 1.25V, 1.375V) • Four Shared Analog Input Channels – Configure as Multiple Input Window Comparator • ...
Page 127
... ACSRA and ACSRB. When changing the analog 1-0 1 Disable comparator interrupts ACSRA, #0DFh ; Clear CONA to disconnect COMP A ; Modify CSA or RFA bits ACSRA, #020h ; Set CONA to connect COMP A ACSRA, #0EFh ; Clear any spurious interrupt EC ; Re-enable comparator interrupts AT89LP6440 - Preliminary 47. The flags may be 2-0. Figure 20-3. An analog source 127 ...
Page 128
... Therefore, after the initial edge event, the interrupt may occur between 1 and 2 time-out periods later. See flows, i.e. CxC be accepted as an edge event. Figure 19-3. Negative Edge with Debouncing Example Comparator Out Timer 1 Overflow AT89LP6440 - Preliminary 128 kΩ AINn C ...
Page 129
... A CMPA - + A CMPA - + AIN3 CMPA AIN2 CSB = 11 RFB = 00 + AIN3 CMPA AREF CSB = 11 RFB = 10 AT89LP6440 - Preliminary f. 2-channel window comparator with external reference CMPB - AIN2 B + AIN0 AIN3 + A - AIN1 CSA = CSB = 00/11 RFA = RFB = 00 g. 4-channel window comparator with internal reference - V AREF+Δ B AIN0 ...
Page 130
... Notes: 1. CONA must be cleared to 0 before changing CSA[1-0]. 2. Debouncing modes require the use of Timer 1 to generate the sampling delay. AT89LP6440 - Preliminary 130 CONA CFA CENA (1) Interrupt Mode Negative (Low) level Positive edge (2) Toggle with debouncing (2) Positive edge with debouncing Negative edge ...
Page 131
... AIN2 (P2.6) AIN3 (P2.7) CMB0 Interrupt Mode 0 Negative (Low) level 1 Positive edge (2) 0 Toggle with debouncing 1 Positive edge with debouncing 0 Negative edge 1 Toggle 0 Negative edge with debouncing 1 Positive (High) level AT89LP6440 - Preliminary Reset Value = 1100 0000B CENB CMB2 CMB1 (2) (2) CMB0 0 131 ...
Page 132
... RFA0 A- Channel 0 0 AIN1 (P2. Internal Internal Internal V Notes: 1. CONB (ACSRB.5) must be cleared to 0 before changing RFB[1-0]. 2. CONA (ACSRA.5) must be cleared to 0 before changing RFA[1-0]. AT89LP6440 - Preliminary 132 RFB1 RFB0 CAC1 (1) (~1.125V) AREF-Δ (~1.25V) AREF (~1.375V) AREF+Δ (2) (~1.125V) AREF-Δ ...
Page 133
... Digital-to-Analog/Analog-to-Digital Converter The AT89LP6440 includes a 10-bit Data Converter (DADC) with the following features: • Digital-to-Analog (DAC) or Analog-to-Digital (ADC) Mode • 10-bit Resolution • 6.5 µs Conversion Time • 8 Multiplexed Single-ended Channels or 4 Differential Channels • Selectable 1.0V±10% Internal Reference Voltage • ...
Page 134
... AVDD R R AGND INTERNAL 1.0V REFERENCE ADC7 ADC6 ADC5 ADC4 POS. INPUT ADC3 ADC2 ADC1 ADC0 NEG. INPUT AVDD/2 AT89LP6440 - Preliminary 134 Example ADC Conversion Codes Left Adjust Single-Ended Mode (V 0 4000h 1 7FC0h 511/512 C000h AV /2 – 1 8040h AV /2 – 511/512 x V ...
Page 135
... To achieve 10-bit resolution the S/H capacitor must be charged to within 1/2 LSB of the expected value within the 1 ADC clock period sample time. High impedance sources may require a reduction in the ADC clock frequency to achieve full resolution. 3706A–MICRO–9/09 AT89LP6440 - Preliminary minus 1 LSB. REF One Conversion ...
Page 136
... Figure 20-4. DAC Timing Diagram Cycle Number ADC Clock GO/BSY ADIF DADH DADL The equivalent model for the analog output circuitry is illustrated in put resistance of the DAC must drive the pin capacitance and any external load on the pin. AT89LP6440 - Preliminary 136 kΩ ADCn C = ...
Page 137
... Alternatively, a conversion can be started automatically by various timer sources. Conversion trigger sources are selected by the TRG bits in DADI. A conversion is started every time the selected timer overflows, allowing for conversions to occur at fixed intervals. The GO/BSY bit will 3706A–MICRO–9/09 AT89LP6440 - Preliminary R = OUT 100 kΩ ...
Page 138
... Place the CPU in Idle during a conversion. • If any Port 0 pins are used as digital outputs essential that these do not switch while a conversion is in progress. Figure 20-7. Example ADC Power Connections (TQFP Package) AT89LP6440 - Preliminary 138 pin to the digital V supply voltage via an LC network as shown in ...
Page 139
... ADC.5 ADC ADC.13 ADC.12 ADC. AT89LP6440 - Preliminary Reset Value = 0000 0000B LADJ ACK2 ACK1 Reset Value = 0000 0000B ADC.3 ADC.2 ADC Reset Value = 0000 0000B ADC.10 ADC ACK0 0 ADC.0 0 ADC.8 0 139 ...
Page 140
... ACS [2-0] DADC Channel Select DIFF ACS2 ACS1 AT89LP6440 - Preliminary 140 TRG1 TRG0 DIFF ACS0 P0.0 AVDD/2 1 P0.1 AVDD/2 0 P0.2 AVDD/2 1 P0.3 AVDD/2 0 P0.4 AVDD/2 1 P0.5 AVDD/2 0 P0.6 AVDD/2 1 P0.7 AVDD/2 0 P0.0 P0.1 1 P0.2 P0.3 0 P0.4 P0.5 1 P0.6 P0.7 0 reserved 1 reserved 0 reserved ...
Page 141
... Watchdog Timer Time-out Period Selection WDT Prescaler Bits PS2 PS1 The WDT time-out period is dependent on the system clock frequency. ------------------------------------------------------ - Time-out Period = Oscillator Frequency MOV WDTRST, #01Eh MOV WDTRST, #0E1h AT89LP6440 - Preliminary (1) Period PS0 (Clock Cycles) 0 16K 1 32K 0 64K 1 128K 0 256K 1 512K 0 1024K 1 2048K ( ) × ...
Page 142
... Software Reset A Software Reset of the AT89LP6440 is accomplished by writing the software reset sequence 5AH/A5H to the WDTRST SFR. The WDT does not need to be enabled to generate the software reset. A normal software reset will set the SWRST flag in WDTCON. However any time an incorrect sequence is written to WDTRST (i.e. anything other than 1EH/E1H or 5AH/A5H), a software reset will immediately be generated and both the SWRST and WDTOVF flags will be set ...
Page 143
... The AT89LP6440 is fully binary compatible with the 8051 instruction set. The difference between the AT89LP6440 and the standard 8051 is the number of cycles required to execute an instruction. Instructions in the AT89LP6440 may take clock cycles to complete. The exe- cution times of most instructions may be computed using Table 22-1 ...
Page 144
... Logical CLR A CPL A ANL A, Rn ANL A, direct ANL A, @Ri ANL A, #data ANL direct, A ANL direct, #data ORL A, Rn ORL A, direct ORL A, @Ri ORL A, #data ORL direct, A ORL direct, #data XRL A, Rn AT89LP6440 - Preliminary 144 Instruction Execution Times and Exceptions (Continued Bytes 1 2 ...
Page 145
... MOV @Ri, #data MOV DPTR, #data16 MOV /DPTR, #data16 MOVC A, @A+DPTR MOVC A, @A+/DPTR MOVC A, @A+PC MOVX A, @Ri MOVX A, @DPTR MOVX A, @/DPTR MOVX @Ri, A MOVX @DPTR, A MOVX @/DPTR, A PUSH direct 3706A–MICRO–9/09 AT89LP6440 - Preliminary Instruction Execution Times and Exceptions (Continued Bytes 1 ...
Page 146
... JMP @A+DPTR JMP @A+PC CJNE A, direct, rel CJNE A, #data, rel CJNE Rn, #data, rel CJNE @Ri, #data, rel CJNE A, @R0, rel CJNE A, @R1, rel DJNZ Rn, rel DJNZ direct, rel NOP (1)(3) BREAK Notes: AT89LP6440 - Preliminary 146 Instruction Execution Times and Exceptions (Continued Bytes ...
Page 147
... If OCD is disabled, BREAK acts as a double NOP. No flags are affected. Example: If On-Chip Debugging is allowed, the following instruction, BREAK will halt instruction execution prior to the immediately following instruction. If debugging is not allowed, the BREAK is treated as a double NOP. Bytes: 2 Cycles: 2 Encoding: A5 Operation: BREAK (PC) ← (PC 3706A–MICRO–9/09 AT89LP6440 - Preliminary ...
Page 148
... CLR M Function: Clear MAC Accumulator Description: CLR M clears the 40-bit M register. No flags are affected. Example: The M registercontains 123456789AH. The following instruction, CLR M leaves the M register set to 0000000000H. Bytes: 2 Cycles: 2 Encoding: A5 Operation: JMP (M) ← 0 AT89LP6440 - Preliminary 148 ...... ...... ; ACC = @R0. ...... ...... ;ACC > @R0 ...
Page 149
... AJMP LABEL2 AJMP LABEL3 If the Accumulator equals 04H when starting this sequence, execution jumps to label LABEL2. Because AJMP is a 2-byte instruction, the jump instructions start at every other address. Bytes: 2 Cycles: 3 Encoding: A5 Operation: JMP (PC) ← (A) + (PC 3706A–MICRO–9/ AT89LP6440 - Preliminary 149 ...
Page 150
... MOVC A, @A+PC RET TABLE: DB 66H DB 77H DB 88H DB 99H If the subroutine is called with the Accumulator equal to 01H, it returns with 77H in the Accumulator. Bytes: 2 Cycles: 4 Encoding: A5 Operation: MOVC IF (DPS THEN (A) ← ( (A) + (DPTR1) ) ELSE (A) ← ( (A) + (DPTR0) ) AT89LP6440 - Preliminary 150 3706A–MICRO–9/09 ...
Page 151
... Data Pointer: DPH1 hold 56H and DPL1 holds 78H. Bytes: 2 Cycles: 3 Encoding: A5 Operation: MOV IF (DPS THEN (DP1H) ← #data (DP1L) ← #data ELSE (DP0H) ← #data (DP0L) ← #data 3706A–MICRO–9/09 AT89LP6440 - Preliminary immed. data 15-8 15-8 7-0 15-8 7 immed ...
Page 152
... Example: DPS = 0, DPTR0 contains 0123H and DPTR1 contains 4567H. The following instruction sequence, MOVX A, @DPTR MOVX @/DPTR, A copies the data from address 0123H to 4567H. Bytes: 2 Cycles: 3 (EDATA) 5 (FDATA or XDATA) Encoding: A5 Operation: MOVX IF (DPS THEN ((DPTR1)) ← (A) ELSE ((DPTR0)) ← (A) AT89LP6440 - Preliminary 152 3706A– ...
Page 153
... IE2 IP IP2 IPH IPH2 MACH MACL MEMCON P0 P0M0 P0M1 3706A–MICRO–9/09 AT89LP6440 - Preliminary Special Function Register Cross Reference Address Description Index E0H 97H Table 19-1 on page 130 9FH Table 19-2 on page 131 AFH Table 19-3 on page 132 8EH Table 3-4 on page 17 E1H Section 5 ...
Page 154
... SP SPCR SPDR SPSR SPX T2CCA T2CCC T2CCF T2CCH T2CCL T2CON T2MOD TCON TCONB AT89LP6440 - Preliminary 154 Special Function Register Cross Reference 90H Table 10-3 on page 44 C2H Table 10-2 and Table 10-3 on page 44 C3H Table 10-2 and Table 10-3 on page 44 A0H Table 10-3 on page 44 ...
Page 155
... WDTCON WDTRST 24. On-Chip Debug System The AT89LP6440 On-Chip Debug (OCD) System uses a two-wire serial interface to control pro- gram flow; read, modify, and write the system state; and program the nonvolatile memory. The OCD System has the following features: • Complete program flow control • ...
Page 156
... OCD is disabled. 24.3 Limitations of On-Chip Debug The AT89LP6440 is a fully-featured microcontroller that multiplexes several functions on its lim- ited I/O pins. Some device functionality must be sacrificed to provide resources for On-Chip Debugging. The On-Chip Debug System has the following limitations: • The Debug Clock pin (DCL) is physically located on that same pin as Port Pin P4.2 and the External Reset (RST) ...
Page 157
... SPI master, and the target system always oper- ates as the SPI slave. To enter or remain in Programming mode the device’s reset line (RST) must be held active (low). With the addition of VDD and GND, an AT89LP6440 microcontroller can be programmed with a minimum of seven connections as shown in 3706A– ...
Page 158
... Figure 25-2. Parallel Programming Device Connections The Programming Interface is the only means of externally programming the AT89LP6440 microcontroller. The Interface can be used to program the device both in-system and in a stand- alone serial programmer. The Interface does not require any clock other than SCK and is not limited by the system clock frequency ...
Page 159
... The ISP interface uses the SPI clock mode 0 (CPOL = 0, CPHA = 0) exclusively with a maximum frequency of 5 MHz. • The AT89LP6440 will enter programming mode only when its reset line (RST) is active (low). To simplify this operation recommended that the target reset can be controlled by the In- System programmer ...
Page 160
... Page oriented instructions always include a full 16-bit address. The higher order bits select the page and the lower order bits select the byte within that page. The AT89LP6440 allocates 6 bits for byte address, 1 bit for low/high half page selection and 9 bits for page address. The half page to be accessed is always fixed by the page address and half select as transmitted ...
Page 161
... Input Address Low Byte Input/Output Address +1 Data Preamble 2 Opcode Address High X X WRITE 55h Opcode Address High READ 55h Opcode Address High AT89LP6440 - Preliminary Table 25-2 on page 162 Address Low Data Data Out Address Low Data In Address Low 0 0 Data Out 161 ...
Page 162
... AT89LP6440: 1EH 8. Symbol Key: a: Page Address Bit s: Half Page Select Bit b: Byte Address Bit x: Don’t Care Bit AT89LP6440 - Preliminary 162 Opcode Addr High 1010 1100 0101 0011 1010 1100 0011 0101 1000 1010 0110 0000 xxxx xxxx 0101 0001 ...
Page 163
... Flash Security The AT89LP6440 provides two Lock Bits for Flash Code and Data Memory security. Lock bits can be left unprogrammed (FFh) or programmed (00h) to obtain the protection levels listed in Table 25-4 ...
Page 164
... User Configuration Fuses The AT89LP6440 includes 11 user fuses for configuration of the device. Each fuse is accessed at a separate address in the User Fuse Row as listed in gramming 00h to their locations. Programming FFh to a fuse location will cause that fuse to maintain its previous state. To set a fuse (set to FFh) the fuse row must be erased and then reprogrammed using the Fuse Write with Auto-erase command ...
Page 165
... The second page of the User Signature Array (0080H–00FFH) contains analog configuration parameters for the AT89LP6440. Each byte represents a parameter as listed in is preset in the factory. The parameters are read at POR and the device is configured accord- ingly. The second page of the array is not affected by Chip Erase. Other bytes in this page may be used as additional signature space ...
Page 166
... ISP Start Sequence Execute this sequence to exit CPU execution mode and enter ISP mode when the device has passed Power-On Reset and is already operational. 1. Drive RST low. 2. Drive SS high. 3. Wait t 4. Start programming session. AT89LP6440 - Preliminary 166 PWRUP RST SS SCK ...
Page 167
... V DD XTAL1 RST t SS SSZ t SSD SCK MISO MOSI The waveforms on this page are not to scale. Figure 25-11. The SCK phase and polarity follow SPI clock mode 0 (CPOL = 0, AT89LP6440 - Preliminary t RLZ t t STL ZSS t SSE HIGH Z HIGH Z t RHZ HIGH Z HIGH Z ...
Page 168
... CPHA = 0) where bits are sampled on the rising edge of SCK and output on the falling edge of SCK. For more detailed timing information see Figure 25-11. ISP Byte Sequence Figure 25-12. Serial Programming Interface Timing SS SCK MISO MOSI Figure 25-13. Parallel Programming Interface Timing SS SCK OE P0 AT89LP6440 - Preliminary 168 SCK MOSI MISO Data Sampled t ...
Page 169
... SS Disable Lag Time SSD SCK Setup to SS Low ZSS SCK Hold after SS High SSZ Write Cycle Time WR Write Cycle with Auto-Erase Time Chip Erase Cycle Time ERS independent SCK CLCL AT89LP6440 - Preliminary 25-8, Figure 25-9, Figure 25-10, Figure 25-12 Min Max 100 ...
Page 170
... Power-down is 2V All characteristics contained in this datasheet are based on simulation and characterization of other microcontrollers manu- factured in the same process technology. These values are preliminary values representing design targets, and will be updated after characterization of actual silicon. AT89LP6440 - Preliminary 170 *NOTICE: Condition mA ...
Page 171
... Vcc (V) Idle Supply Current vs. Vcc 8MHz Internal Oscillator 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.0 2.5 3.0 3.5 Vcc (V) AT89LP6440 - Preliminary 4.0 4.5 5.0 5.5 4.0 4.5 5.0 5.5 85C -40C 25C 85C -40C 25C 171 ...
Page 172
... Supply Current (External Clock) Figure 26-3. Active Supply Current vs. Frequency Figure 26-4. Idle Supply Current vs. Frequency Note: AT89LP6440 - Preliminary 172 Active Supply Current vs. Frequency External Clock Source Frequency (MHz) Idle Supply Current vs. Frequency External Clock Source Frequency (MHz) All characteristics contained in this datasheet are based on simulation and characterization of other microcontrollers manufactured in the same process technology ...
Page 173
... Brown-Out Detector Threshold BOD V Brown-Out Detector Hysteresis BH t Power-On Reset Delay POR t Watchdog Reset Pulse Width WDTRST 3706A–MICRO–9/09 AT89LP6440 - Preliminary = -40°C to 85°C and V = 2.4 to 3.6V, unless otherwise noted 2.0V to 3.6V DD Min Max Condition Low Speed Oscillator High Speed Oscillator T = 25° ...
Page 174
... Parameter t applies only when ALES = 1. LHLL 4. The strobe pulse width may be lengthened additional t 5. Parameter t applies only when ALES = 0, or when two MOVX instructions occur in succession. WHLH AT89LP6440 - Preliminary 174 = -40°C to 85°C and V = 2.4 to 3.6V, unless otherwise noted. Under oper (5) ...
Page 175
... A8 - A15 FROM DPH OR P2.0 - P2.7 t LHLL t t LLWL WLWH t QVWX t LLAX DATA OUT t QVWH t AVWL A8 - A15 FROM DPH OR P2.0 - P2.7 = -40°C to 85°C and V A AT89LP6440 - Preliminary t WHLH t t RLDV RHDZ t RHDX DATA IN t WHAX P2 t WHLH t WHQX t WHAX P2 = 2.4 to 3.6V, unless otherwise noted. ...
Page 176
... SOV t Output Enable Time SOE t Output Disable Time SOX t Slave Enable Lead Time SSE t Slave Disable Lag Time SSD Figure 26-8. SPI Master Timing (CPHA = 0) SS SCK (CPOL = 0) SCK (CPOL = 1) MISO MOSI AT89LP6440 - Preliminary 176 Min 10 Min 41.6 4t CLCL 1 CLCL 1 CLCL ...
Page 177
... MISO MOSI Figure 26-11. SPI Slave Timing (CPHA = 1) SS SCK (CPOL = 0) SCK (CPOL = 1) MISO MOSI 3706A–MICRO–9/ SCK SSE t t SHSL SLSH t t SLSH SHSL SOV SOH SOE t SF AT89LP6440 - Preliminary t t SSD SF t SOX t t SIS SIH SOV 177 ...
Page 178
... Two-wire Serial Interface Characteristics Table 26-7 describes the requirements for devices connected to the Two-wire Serial Bus. The AT89LP6440 Two-wire Serial Interface meets or exceeds these requirements under the noted conditions. The values shown in this table are valid for T = -40°C to 85°C and ...
Page 179
... Load Capacitance = 80 pF. DD SMOD1 = 0 Min 4t -15 CLCL 3t -15 CLCL t -15 CLCL 0 15 SMOD1 = Valid Valid Valid SMOD1 = Valid Valid Valid AT89LP6440 - Preliminary SU;DAT t SU;STO SMOD1 = 1 Max Min Max 2t -15 CLCL t -15 CLCL t -15 CLCL Valid Valid Valid Valid ...
Page 180
... Differential Input Common V CMI Mode Voltage V Differential Input Voltage DI R Analog Input Resistance IN R Analog Mux Resistance MUX C Sample & Hold Capacitance S/H AT89LP6440 - Preliminary 180 = -40°C to 85°C and V = 2.4 to 3.6V, unless otherwise noted Condition – 20mV 2.4V IN+ IN -40° ...
Page 181
... Condition ≥ ACK CLCL External Reference AV Internal Reference AV AV (1) - 0.5V for a logic “1” and 0.45V for a logic “0”. Timing measurements are made at DD max. for a logic “0” level occurs AT89LP6440 - Preliminary Min Typical 10 500 12t 11t ACK 0 0 ...
Page 182
... Test Condition, Active Mode, All Other Pins are Disconnected CC 26.12.4 I Test Condition, Idle Mode, All Other Pins are Disconnected CC 26.12.5 Clock Signal Waveform for 0.5V CC 0.45V 26.12.6 I Test Condition, Power-down Mode, All Other Pins are Disconnected AT89LP6440 - Preliminary 182 RST XTAL2 (NC) CLOCK SIGNAL XTAL1 GND ...
Page 183
... Wide, Plastic Dual Inline Package (PDIP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 44M1 44-pad 1.0 mm Body, Plastic Very Thin Quad Flat No Lead Package (VQFN/MLF) 3706A–MICRO–9/09 Ordering Code AT89LP6440-20AU AT89LP6440-20PU AT89LP6440-20JU AT89LP6440-20MU Package Types AT89LP6440 - Preliminary Package Operation Range 44A 40P6 Industrial 44J (-40° ...
Page 184
... This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT89LP6440 - Preliminary 184 TITLE 44A, 44-lead Body Size, 1 ...
Page 185
... Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R 3706A–MICRO–9/09 D PIN 0º ~ 15º REF eB TITLE 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) AT89LP6440 - Preliminary E1 A1 COMMON DIMENSIONS (Unit of Measure = mm) MIN SYMBOL NOM A – – A1 0.381 – D 52.070 – ...
Page 186
... Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT89LP6440 - Preliminary 186 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER E1 E ...
Page 187
... Chamfer (C 0.30) Option C Pin #1 Notch e (0.20 R) TITLE 44M1, 44-pad 1.0 mm Body, Lead Pitch 0.50 mm, 5.20 mm Exposed Pad, Thermally Enhanced Plastic Very Thin Quad Flat No Lead Package (VQFN) AT89LP6440 - Preliminary SEATING PLANE SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM A 0 ...
Page 188
... Revision History Revision No. Revision A – September 2009 AT89LP6440 - Preliminary 188 History • Initial Release 3706A–MICRO–9/09 ...
Page 189
... Enhanced Dual Data Pointers .........................................................................24 5.3 Instruction Set Extensions ...............................................................................29 6.1 Crystal Oscillator .............................................................................................30 6.2 External Clock Source .....................................................................................31 6.3 Internal RC Oscillator ......................................................................................31 6.4 System Clock Out ............................................................................................31 6.5 System Clock Divider ......................................................................................31 7.1 Power-on Reset ...............................................................................................32 7.2 Brown-out Reset ..............................................................................................34 7.3 External Reset .................................................................................................34 7.4 Watchdog Reset ..............................................................................................35 AT89LP6440 - Preliminary i ...
Page 190
Software Reset ................................................................................................35 8 Power Saving Modes ............................................................................. 35 8.1 Idle Mode .........................................................................................................35 8.2 Power-down Mode ...........................................................................................36 8.3 Reducing Power Consumption ........................................................................37 9 Interrupts ................................................................................................ 38 9.1 Interrupt Response Time .................................................................................40 10 I/O Ports .................................................................................................. 44 10.1 Port Configuration ...
Page 191
Serial Interface (UART) .......................................................................... 84 17 Enhanced Serial Peripheral Interface .................................................. 97 18 Two-Wire Serial Interface .................................................................... 104 19 Dual Analog Comparators ................................................................... 126 20 Digital-to-Analog/Analog-to-Digital Converter .................................. 133 3706A–MICRO–9/09 16.1 Multiprocessor Communications .....................................................................84 16.2 Baud Rates ......................................................................................................86 16.3 ...
Page 192
Programmable Watchdog Timer ......................................................... 141 21.1 Software Reset ..............................................................................................142 22 Instruction Set Summary .................................................................... 143 22.1 Instruction Set Extensions .............................................................................147 23 Register Index ...................................................................................... 153 24 On-Chip Debug System ....................................................................... 155 24.1 Physical Interface ..........................................................................................155 24.2 Software Breakpoints ....................................................................................156 ...
Page 193
Ordering Information ........................................................................... 183 28 Packaging Information ........................................................................ 184 29 Revision History ................................................................................... 188 3706A–MICRO–9/09 27.1 Green Package Option (Pb/Halide-free) ........................................................183 28.1 44A – TQFP ...................................................................................................184 28.2 40P6 – PDIP ..................................................................................................185 28.3 44J – PLCC ...................................................................................................186 28.4 44M1 – ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...