AT89LP6440-20JU Atmel, AT89LP6440-20JU Datasheet - Page 44

• Manufacturer Part Number: AT89LP6440-20JU
• Description: MCU 8051 64K FLASH ISP 44PLCC
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP6440-20JU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10. I/O Ports
10.1
44
Port Configuration
AT89LP6440 - Preliminary
The AT89LP6440 can be configured for between 35 and 38 I/O pins. The exact number of I/O
pins available depends on the clock and reset options as shown in
Table 10-1.
All port pins on the AT89LP6440 may be configured to one of four modes: quasi-bidirectional
(standard 8051 port outputs), push-pull output, open-drain output, or input-only. Port modes may
be assigned in software on a pin-by-pin basis as shown in
Table
fuse is enabled, all port pins default to input-only mode after reset. When the fuse is disabled, all
port pins, with the exception of the analog inputs, P0.7-0, P2.4, P2.5, P2.6 and P2.7, default to
quasi-bidirectional mode after reset and are weakly pulled high. The analog input pins always
reset to input-only (tristate) mode. Each port pin also has a Schmitt-triggered input for improved
input noise rejection. During Power-down all the Schmitt-triggered inputs are disabled with the
exception of P3.2 (INT0), P3.3 (INT1), P4.2 (RST), P4.0 (XTAL1) and P4.1 (XTAL2) which may
be used to wake up the device. Therefore, P3.2, P3.3, P4.2, P4.0 and P4.1 should not be left
floating during Power-down. In addition any pin of Port 1 configured as a General-Purpose inter-
rupt input will also remain active during Power-down to wake-up the device. These interrupt pins
should either be disabled before entering Power-down or they should not be left floating.
.
Table 10-2.
.
Table 10-3.
Clock Source
External Crystal or
Resonator
External Clock
Internal RC Oscillator
PxM0.y
10-3. The Tristate-Port User Fuse determines the default state of the port pins. When the
Port
0
0
1
1
0
1
2
3
4
I/O Pin Configurations
Configuration Modes for Port x, Bit y
Port Configuration Registers
Port Data
P4 (C0H)
P2 (A0H)
P3 (B0H)
P0 (80H)
P1 (90H)
PxM1.y
0
1
0
1
Reset Option
External RST Pin
No external reset
External RST Pin
No external reset
External RST Pin
No external reset
Port Mode
Quasi-bidirectional
Push-pull Output
Input Only (High Impedance)
Open-Drain Output
Port Configuration
P0M0 (BAH), P0M1 (BBH)
P1M0 (C2H), P1M1 (C3H)
P2M0 (C4H), P2M1 (C5H)
P3M0 (C6H), P3M1 (C7H)
P4M0 (BEH), P4M1 (BFH)
Number of I/O Pins
Table 10-2
35
36
36
37
37
38
Table
using the registers listed in
10-1.
3706A–MICRO–9/09