AT89LP6440-20JU Atmel, AT89LP6440-20JU Datasheet - Page 23

• Manufacturer Part Number: AT89LP6440-20JU
• Description: MCU 8051 64K FLASH ISP 44PLCC
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP6440-20JU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.1
3706A–MICRO–9/09
Multiply–Accumulate Unit (MAC)
Figure 5-3.
The AT89LP6440 includes a multiply and accumulate (MAC) unit that can significantly speed up
many mathematical operations required for digital signal processing. The MAC unit includes a
16-by-16 bit multiplier and a 40-bit adder that can perform integer or fractional multiply-accumu-
late operations on signed 16-bit input values. The MAC unit also includes a 1-bit arithmetic
shifter that will left or right shift the contents of the 40-bit MAC accumulator register (M).
A block diagram of the MAC unit is shown in
vided by the register pairs (AX,ACC) and (BX,B) where AX (E1H) and BX (F7H) hold the higher
order bytes. The 16-by-16 bit multiplication is computed through partial products using the
AT89LP6440’s 8-bit multiplier. The 32-bit signed product is added to the 40-bit M accumulator
register. The MAC operation is summarized as follows:
All computation is done in signed two’s complement form.
Figure 5-4.
Fetch Immediate Operand
ALU Operation Execute
Fetch Next Instruction
Total Execution Time
Result Write Back
Two-cycle ALU Operation (Example: ADD A, #data)
Multiply–Accumulate Unit
System Clock
SMLA
SMLB
MRW
PSW
MAC AB:
AX
M4
8 x 8-bit Signed MULT
ACC
M
M3
←
T
M
AT89LP6440 - Preliminary
1
Figure
+
40-bit ADD
{
AX ACC
BX
M2
,
5-4. The 16-bit signed operands are pro-
}
MACH
×
B
M1
T
{
BX B
2
Shifter
, }
MACL
M0
T
3
23