AT89LP6440-20JU Atmel, AT89LP6440-20JU Datasheet - Page 33

• Manufacturer Part Number: AT89LP6440-20JU
• Description: MCU 8051 64K FLASH ISP 44PLCC
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP6440-20JU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3706A–MICRO–9/09
generated reset can be extended beyond the power-on period by holding the RST pin low longer
than the time-out.
Figure 7-1.
If the Brown-out Detector (BOD) is also enabled, the start-up timer does not begin counting until
after V
occurs prior to the end of the initialization sequence, the timer must first wait for that sequence to
complete before counting.
Figure 7-2.
Note:
The start-up timer delay is user-configurable with the Start-up Time User Fuses and depends on
the clock source
after a Brown-out Reset or when waking up from Power-down during internally timed mode. The
start-up delay should be selected to provide enough settling time for V
source. The device operating environment (supply voltage, frequency, temperature, etc.) must
Time-out
Time-out
Internal
Internal
Internal
Internal
DD
Reset
Reset
Reset
Reset
RST
RST
t
V
POR
RST
RST
reaches the BOD threshold voltage V
V
DD
DD
is approximately 143 µs ± 5%.
Power-on Reset Sequence (BOD Disabled)
Power-on Reset Sequence (BOD Enabled)
t
POR
(Table
V
POR
7-1). The Start-Up Time fuses also control the length of the start-up time
(RST Controlled Externally)
(RST Controlled Externally)
V
V
BOD
POR
t
POR
+ t
SUT
t
SUT
AT89LP6440 - Preliminary
BOD
(RST Tied to V
(RST Tied to V
as shown in
t
RHD
CC
Figure
V
CC
)
V
IH
IH
)
V
POR
t
RHD
7-2. However, if this event
DD
and the selected clock
33