AT89LP6440-20JU Atmel, AT89LP6440-20JU Datasheet - Page 20

• Manufacturer Part Number: AT89LP6440-20JU
• Description: MCU 8051 64K FLASH ISP 44PLCC
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP6440-20JU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.5
20
In-Application Programming (IAP)
AT89LP6440 - Preliminary
separate copies of SP for use with each stack space. Interrupts should be disabled while swap-
ping copies of SP in such an application to prevent illegal stack accesses.
All interrupt calls and PUSH, POP, ACALL, LCALL, RET and RETI instructions will incur a one
or two-cycle penalty while the extended stack is enabled, depending on the number of stack
access in each instruction. The extended stack may only exist within the internal EDATA space;
it cannot be placed in XDATA. The stack will continue to use EDATA even if EDATA is disabled
by setting EXRAM = 1.
Figure 3-14. Stack Configurations
The AT89LP6440 supports In-Application Programming (IAP), allowing the program memory to
be modified during execution. IAP can be used to modify the user application on the fly or to use
program memory for nonvolatile data storage. The same page structure write protocol for
FDATA also applies to IAP (See
always placed in idle while modifying the program memory. When the write completes, the CPU
will continue executing with the instruction after the MOVX @DPTR,A instruction that started the
write.
To enable access to the program memory, the IAP bit (MEMCON.7) must be set to one and the
IAP User Fuse must be enabled. The IAP User Fuse can disable all IAP operations. When this
fuse is disabled, the IAP bit will be forced to 0. While IAP is enabled, all MOVX @DPTR instruc-
tions will access the CODE space instead of EDATA/FDATA/XDATA. IAP also allows
reprogramming of the User Signature Array when SIGEN = 1. The IAP access settings are sum-
marized in
Table 3-5.
IAP
0
0
0
0
1
1
Table
SIGEN
IAP Access Settings
0
0
1
1
0
1
3-5.
7
DMEN
SP
X
X
0
1
0
1
0
FFh
00h
XSTK = 0
IDATA
Section 3.3.3.1 “Write Protocol” on page
(256)
EDATA (0000–0FFFH)
FDATA (1000–2FFFH)
EDATA (0000–0FFFH)
FDATA (1000–2FFFH)
CODE (0000–FFFFH)
SIG (0000–01FFH)
MOVX @DPTR
3
SPX
0
7
SP
0
FFFh
00h
XSTK = 1
EDATA
(4K)
CODE (0000–FFFFH)
CODE (0000–FFFFH)
CODE (0000–FFFFH)
SIG (0000–01FFH)
SIG (0000–01FFH)
SIG (0000–01FFH)
MOVC @DPTR
13). The CPU is
3706A–MICRO–9/09