AT89LP6440-20JU Atmel, AT89LP6440-20JU Datasheet - Page 73

• Manufacturer Part Number: AT89LP6440-20JU
• Description: MCU 8051 64K FLASH ISP 44PLCC
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP6440-20JU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 13-5.
Notes:
3706A–MICRO–9/09
T2CCC Address = 0D4H
Not Bit Addressable
Bit
Symbol
CIENx
CDIRx
CTCx
CCMx
CxM[2-0]
1. All writes/reads to/from T2CCC will access channel X as currently selected by T2CCA.The control registers for the remain-
2. Analog Comparator A events are determined by the CMA
3. Analog Comparator B events are determined by the CMB
4. Asymmetrical versus Symmetrical PWM is determined by the Timer 2 Count Mode. See
CIENx
ing unselected channels are not accessible.
7
Function
Channel X Interrupt Enable. When set, channel X’s interrupt flag, CCFx in T2CCF, will generate an interrupt when ECC
= 1. Clear to disable interrupts from channel X.
Channel X Capture Direction. In dual-slope modes, a compare/capture event on channel X will store the current count
direction into CDIRx. Up-counting = 0 and down-counting = 1. Modifying this bit has no effect.
Clear Timer on Compare/Capture of Channel X. When set, the Timer 2 registers TL2 and TH2 will be cleared by a
compare/capture event on channel X. When cleared, Timer 2 is unaffected by channel X events.
Channel X Compare/Capture Mode. When CCMx = 1, channel X operates in compare mode. When CCMx = 0, channel
X operates in capture mode.
Channel X Mode. Selects the output/input events for compare/capture channel X.
CxM2
0
0
0
0
1
1
1
1
CxM2
0
0
0
0
1
1
1
1
T2CCC – Timer/Counter 2 Compare/Capture Control
CxM1
0
0
1
1
0
0
1
1
CxM1
0
0
1
1
0
0
1
1
CDIRx
6
CxM0
0
1
0
1
0
1
0
1
CxM0
0
1
0
1
0
1
0
1
–
5
Capture Event (CCMx = 0)
Disabled
Trigger on negative edge of CCx pin
Trigger on positive edge of CCx pin
Trigger on either edge of CCx pin
Trigger on Timer 0 overflow
Trigger on Timer 1 overflow
Trigger on Analog Comparator A Event
Trigger on Analog Comparator B Event
Compare Action (CCMx = 1)
Output disabled (interrupt only)
Set CCx pin on compare match
Clear CCx pin on compare match
Toggle CCx pin on compare match
Inverting Pulse Width Modulation
Non-Inverting Pulse Width Modulation
Reserved
Reserved
CTCx
4
2-0
2-0
CCMx
bits in ACSRA. See
bits in ACSRB. See
3
AT89LP6440 - Preliminary
(4)
(4)
CxM2
(2)
(3)
2
Table 19-1 on page
Table 19-2 on page
Reset Value = 00X0 0000B
Section 13.4 on page
CxM1
1
130.
131.
CxM0
0
76.
73