HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 181

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 9 Direct Memory Access Controller (DMAC)
9.3.5
Address Modes
Single Address Mode: In the single address mode, both the transfer source and destination are
external; one (selectable) is accessed by a DACK signal while the other is accessed by an address.
In this mode, the DMAC performs the DMA transfer in 1 bus cycle by simultaneously outputting a
transfer request acknowledge DACK signal to one external device to access it while outputting an
address to the other end of the transfer. Figure 9.5 shows a transfer between an external memory
and an external device with DACK in which the external device outputs data to the data bus while
that data is written in external memory in the same bus cycle.
External address bus
External data bus
SuperH microcomputer
External
memory
DMAC
External device
with DACK
DACK
DREQ
: Data flow
Figure 9.5 Data Flow in Single Address Mode
Two types of transfers are possible in the single address mode: (a) transfers between external
devices with DACK and memory-mapped external devices, and (b) transfers between external
devices with DACK and external memory. The only transfer requests for either of these is the
external request (DREQ). Figure 9.6 shows the DMA transfer timing for the single address mode.
Rev. 5.00 Jan 06, 2006 page 159 of 818
REJ09B0273-0500

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