HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 48

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 2 CPU
Delayed Branch Instructions: Unconditional branch instructions are delayed. Executing the
instruction that follows the branch instruction and then branching reduces pipeline disruption
during branching (table 2.3). There are two types of conditional branch instructions: delayed
branch instructions and ordinary branch instructions.
Table 2.3
SH7050 Series CPU
BRA
ADD
Multiplication/Accumulation Operation: 16-bit 16-bit
executed in one to two cycles. 16-bit 16-bit + 64-bit
operations are executed in two to three cycles. 32-bit 32-bit
T Bit: The T bit in the status register changes according to the result of the comparison, and in
turn is the condition (true/false) that determines if the program will branch. The number of
instructions that change the T bit is kept to a minimum to improve the processing speed (table
2.4).
Table 2.4
SH7050 Series CPU
CMP/GE
BT
BF
ADD
CMP/EQ
BT
Rev. 5.00 Jan 06, 2006 page 26 of 818
REJ09B0273-0500
64-bit multiplication/accumulation operations are executed in two to four cycles.
TRGET
R1,R0
R1,R0
TRGET0
TRGET1
#–1,R0
#0,R0
TRGET
Delayed Branch Instructions
T Bit
Description
T bit is set when R0
program branches to TRGET0
when R0
when R0 < R1.
T bit is not changed by ADD. T bit
is set when R0 = 0. The program
branches if R0 = 0.
Description
Executes an ADD before
branching to TRGET
R1 and to TRGET1
R1. The
64-bit multiplication/accumulation
32-bit multiplication operations are
Example of Conventional CPU
ADD.W
BRA
Example of Conventional CPU
CMP.W R1,R0
BGE
BLT
SUB.W #1,R0
BEQ
64-bit and 32-bit
TRGET0
TRGET1
TRGET
R1,R0
TRGET
32-bit + 64bit