HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 487

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.2.4
The compare match timer constant register (CMCOR) is a 16-bit register that sets the compare
match period with the CMCNT.
The CMCOR is initialized to H'FFFF by a power-on reset and in hardware standby mode and
software standby mode. There is no initializing with manual reset.
15.3
15.3.1
When an internal clock is selected with the CKS1, CKS0 bits of the CMCSR register and the STR
bit of the CMSTR is set to 1, the CMCNT begins incrementing with the selected clock. When the
CMCNT counter value matches that of the compare match constant register (CMCOR), the
CMCNT counter is cleared to H'0000 and the CMF flag of the CMCSR register is set to 1. If the
CMIE bit of the CMCSR register is set to 1 at this time, a compare match interrupt (CMI) is
requested. The CMCNT counter begins counting up again from H'0000.
Figure 15.2 shows the compare match counter operation.
Initial value:
Initial value:
Compare Match Timer Constant Register (CMCOR)
Operation
Period Count Operation
R/W:
R/W:
Bit:
Bit:
R/W
R/W
15
1
7
1
R/W
R/W
14
1
6
1
R/W
R/W
13
1
5
1
R/W
R/W
12
1
4
1
Section 15 Compare Match Timer (CMT)
Rev. 5.00 Jan 06, 2006 page 465 of 818
R/W
R/W
11
1
3
1
R/W
R/W
10
1
2
1
REJ09B0273-0500
R/W
R/W
9
1
1
1
R/W
R/W
8
1
0
1