HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 316

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 Advanced Timer Unit (ATU)
10.3.8
The ATU’s channel 0 ICR0A and channel 1 OSBR can be made to perform input capture in
response to the same trigger by means of a setting in timer I/O control register TIOR0A. When the
ATU channel 0 counter (TCNT0) and channel 1 counter (TCNT1) are started by a setting in the
timer status register (TSR), and a trigger signal is input from the ICR0A input capture input pin
(TIA0), the TCNT0 value can be transferred to ICR0A, and the TCNT1 value to OSBR. Rising-
edge, falling-edge, or both-edge detection can be selected for the TIA0 trigger input pin.
By making the appropriate setting in the timer interrupt enable register (TIER), an interrupt
request can be sent to the CPU when input capture occurs.
An example of twin-capture operation is shown in figure 10.19.
In the example in figure 10.19, twin-capture is started using a both-edge detection specification.
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REJ09B0273-0500
Interrupt status
to IIF1by user
H'FFFFFFFF
H'FFFFF800
H'00002800
H'00001800
H'00000800
H'00000000
CPU 0 write
flag (IIF1)
program
Twin-Capture Function
Figure 10.18 Example of Interval Timer Operation
Counter value
TCNT0
Time