HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 516

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 Pin Function Controller (PFC)
16.3.7
The port D IO register (PDIOR) is a 16-bit readable/writable register that selects the input/output
direction of the 16 pins in port D. Bits PD15IOR to PD0IOR correspond to pins PD15/D15 to
PD0/D0. PDIOR is enabled when port D pins function as general input/output pins (PD15 to
PD0), and disabled otherwise.
When port D pins function as PD15 to PD0, a pin becomes an output when the corresponding bit
in PDIOR is set to 1, and an input when the bit is cleared to 0.
PDIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in
hardware standby wode. It is not initialized in software standby mode or sleep mode.
16.3.8
The port D control register (PDCR) is a 16-bit readable/writable register that selects the functions
of the 16 multiplex pins in port D. PDCR settings are not valid in all operating modes.
1. Expanded mode with on-chip ROM disabled (area 0: 8-bit bus)
2. Expanded mode with on-chip ROM disabled (area 0: 16-bit bus)
3. Expanded mode with on-chip ROM enabled
4. Single-chip mode
Rev. 5.00 Jan 06, 2006 page 494 of 818
REJ09B0273-0500
Initial value:
Initial value:
Port D pins D0 to D7 function as data bus input/output pins, and PDCR settings are invalid.
Port D pins function as data bus input/output pins, and PDCR settings are invalid.
Port D pins are multiplexed as data bus input/output pins and general input/output pins. PDCR
settings are valid.
Port D pins function as general input/output pins, and PDCR settings are invalid.
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Bit:
Port D IO Register (PDIOR)
Port D Control Register (PDCR)
PD15
PD15
IOR
MD
15
15
0
0
PD14
PD14
IOR
MD
14
14
0
0
PD13
PD13
IOR
MD
13
13
0
0
PD12
PD12
IOR
MD
12
12
0
0
PD11
PD11
IOR
MD
11
11
0
0
PD10
PD10
IOR
MD
10
10
0
0
PD9
PD9
IOR
MD
9
0
9
0
PD8
PD8
IOR
MD
8
0
8
0
PD7
PD7
IOR
MD
7
0
7
0
PD6
PD6
IOR
MD
6
0
6
0
PD5
PD5
IOR
MD
5
0
5
0
PD4
PD4
IOR
MD
4
0
4
0
PD3
PD3
IOR
MD
3
0
3
0
PD2
PD2
IOR
MD
2
0
2
0
PD1
PD1
IOR
MD
1
0
1
0
PD0
PD0
IOR
MD
0
0
0
0