HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 83

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.1
5.1.1
Exception processing is started by four sources: resets, address errors, interrupts and instructions
and have the priority shown in table 5.1. When several exception processing sources occur at once,
they are processed according to the priority shown.
Table 5.1
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
Exception
Reset
Address
error
Interrupt
Instructions
2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,
Types of Exception Processing and Priority
Overview
BRAF.
BF/S, BT/S, BSRF, BRAF.
Types of Exception Processing and Priority Order
Source
Power-on reset
CPU address error
DMAC address error
NMI
User break
IRQ
On-chip peripheral modules:
Trap instruction (TRAPA instruction)
General illegal instructions (undefined code)
Illegal slot instructions (undefined code placed directly after a delay
branch instruction *
Section 5 Exception Processing
1
or instructions that rewrite the PC *
Direct memory access controller
(DMAC)
Advanced timer unit (ATU)
Compare match timer (CMT)
A/D converter (A/D)
Serial communications interface
(SCI)
Watchdog timer (WDT)
Rev. 5.00 Jan 06, 2006 page 61 of 818
Section 5 Exception Processing
2
)
REJ09B0273-0500
Priority
High
Low