HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 54

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 2 CPU
Addressing
Mode
PC relative
addressing
Immediate
addressing
Rev. 5.00 Jan 06, 2006 page 32 of 818
REJ09B0273-0500
Instruction
Format
disp:8
disp:12
Rn
#imm:8
#imm:8
#imm:8
Effective Addresses Calculation
The effective address is the PC value sign-extended
with an 8-bit displacement (disp), doubled, and
added to the PC value.
The effective address is the PC value sign-extended
with a 12-bit displacement (disp), doubled, and
added to the PC value.
The effective address is the register PC value
plus Rn.
The 8-bit immediate data (imm) for the TST, AND,
OR, and XOR instructions are zero-extended.
The 8-bit immediate data (imm) for the MOV, ADD,
and CMP/EQ instructions are sign-extended.
The 8-bit immediate data (imm) for the TRAPA
instruction is zero-extended and is quadrupled.
(sign-extended)
(sign-extended)
PC
Rn
disp
disp
PC
PC
2
2
+
+
+
PC + disp
PC + disp
PC + Rn
2
2
Equation
PC + disp
PC + disp
PC + Rn
2
2

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