HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 344

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 10 Advanced Timer Unit (ATU)
Sample Setup Procedure for Offset One-Shot Pulse Output: An example of the setup
procedure for offset one-shot pulse output is shown in figure 10.49.
1. Set the first-stage counter clock ' in prescaler register 1 (PSCR1), and select the second-stage
2. Set the port C control register (PCCR) corresponding to the waveform output port to ATU one-
3. Set the one-shot pulse width in the down-counter (DCNT) corresponding to the port set in (2).
4. Set the offset width in the channel 1 or 2 general register (GR1A–GR1F, GR2A, GR2B)
5. Set the CN10A–CN10H bit in the timer connection register (TCNR) corresponding to the port
6. Set the corresponding bit to 1 in the timer start register (TSTR) to start the channel 1 or 2 free-
Rev. 5.00 Jan 06, 2006 page 322 of 818
REJ09B0273-0500
counter clock " with the CKSEL bit in the timer control register (TCR1, TCR2, TCR10).
shot pulse output. Also set the corresponding bit to 1 in the port C IO register (PCIOR) to
specify the output attribute.
If necessary, an interrupt request can be sent to the CPU when the down-counter underflows by
making the appropriate setting in the interrupt enable register (TIERF).
connected to the down-counter (DCNT) corresponding to the port set in (2).
set in (2) to 1.
running counter (TCNT1, TCNT2). When the TCNT value and GR value match, the
corresponding DCNT starts counting down, and one-shot pulse output is performed.

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