HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 828

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Appendix A On-Chip Supporting Module Registers
Bit
13, 12
11–8
6
5
4, 3
2
Rev. 5.00 Jan 06, 2006 page 806 of 818
REJ09B0273-0500
Bit Name
Source address mode
1 and 0 (SM1, SM0)
Resource select
3, 2, 1, and 0
(RS3, RS2, RS1, RS0)
DREQ select (DS)
Transmit mode (TM)
Transmit size 1 and 0
(TS1, TS0)
Interrupt enable (IE)
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
Source address fixed
Source address incremented (+1 for 8-bit transfer, +2 for 16-bit
transfer, +4 for 32-bit transfer)
Source address decremented (–1 for 8-bit transfer, –2 for 16-bit
transfer, –4 for 32-bit transfer)
Setting prohibited
External request, dual address mode
Setting prohibited
External request, single address mode
External address space to external device
External request, single address mode
External device to external address space
Auto-request
Setting prohibited
ATU, compare match 6 (CMI6)
ATU, input capture 0B (ICI0B)
SCI0 transmission
SCI0 reception
SCI1 transmission
SCI1 reception
SCI2 transmission
SCI2 reception
On-chip A/D0
On-chip A/D1
Low level detection
Falling edge detection
Cycle steal mode
Burst mode
Byte size (8 bits)
Word size (16 bits)
Longword size (32 bits)
Setting prohibited
No interrupt request generated at end of number of transfers specified
in DMATCR
Interrupt request generated at end of number of transfers specified in
DMATCR
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)