HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 254

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 Advanced Timer Unit (ATU)
Bit 7—Clear Counter Enable Flag 3B, 3D, 4B, 4D, 5B (CCI3B, CCI3D, CCI4B, CCI4D,
CCI5B): These bits select enabling or disabling of free-running counter (TCNT) clearing.
Bit 7:
CCIxx
0
1
TCNT is cleared on compare-match only when GR is functioning as an output compare register.
Bits 6 to 4—I/O Control 3B2 to 3B0, 3D2 to 3D0, 4B2 to 4B0, 4D2 to 4D0, 5B2 to 5B0 (IO3B2
to IO3B0, IO3D2 to IO3D0, IO4B2 to IO4B0, IO4D2 to IO4D0, IO5B2 to IO5B0): These bits
select the general register (GR) function.
Bit 6:
IOxx2
0
1
Bit 3—Clear Counter Enable Flag 3A, 3C, 4A, 4C, 5A (CCI3A, CCI3C, CCI4A, CCI4C,
CCI5A): These bits select enabling or disabling of free-running counter (TCNT) clearing.
Bit 3:
CCIxx
0
1
TCNT is cleared on compare-match only when GR is functioning as an output compare register.
Rev. 5.00 Jan 06, 2006 page 232 of 818
REJ09B0273-0500
Bit 5:
IOxx1
0
1
0
1
Description
TCNT clearing disabled
TCNT cleared on GR compare-match
Description
TCNT clearing disabled
TCNT cleared on GR compare-match
Bit 4:
IOxx0
0
1
0
1
0
1
0
1
Description
GR is an output
compare register
GR is input capture
register
0 output regardless of compare-match
0 output on GR compare-match
1 output on GR compare-match
Toggle output on GR compare-match
Input capture disabled
Input capture in GR on rising edge
Input capture in GR on falling edge
Input capture in GR on both rising and
falling edges
(Initial value)
(Initial value)
(Initial value)