HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 627

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
19.6.1
When boot mode is used, the flash memory programming control program must be prepared in the
host beforehand. The SCI to be used is set to channel asynchronous mode.
When a reset-start is executed after the SH7051 pins have been set to boot mode, the boot program
built into the SH7051 is started and the programming control program prepared in the host is
serially transmitted to the SH7051 via the channel 1 SCI. In the SH7051, the programming control
program received via the channel 1 SCI is written into the programming control program area in
on-chip RAM. After the transfer is completed, control branches to the start address of the
programming control program area and the programming control program execution state is
entered (flash memory programming is performed).
The transferred programming control program must therefore include coding that follows the
programming algorithm given later.
The system configuration in boot mode is shown in figure 19.3, and the boot mode execution
procedure in figure 19.4.
Boot Mode
Host
Figure 19.3 System Configuration in Boot Mode
Verify data transmission
Write data reception
Rev. 5.00 Jan 06, 2006 page 605 of 818
RXD1
TXD1
Section 19 ROM (256 kB Version)
SCI1
SH7051
Flash memory
On-chip RAM
REJ09B0273-0500

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