HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 424

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 13 Serial Communication Interface (SCI)
Receiving Serial Data (Asynchronous Mode): Figures 13.7 and 13.8 show a sample flowchart
for receiving serial data. The procedure is as follows (the steps correspond to the numbers in the
flowchart).
1. SCI initialization: Set the RxD pin using the PFC.
2. Receive error handling and break detection: If a receive error occurs, read the ORER, PER,
3. SCI status check and receive-data read: Read the serial status register (SSR), check that RDRF
4. Continue receiving serial data: Read the RDR and RDRF bit and clear RDRF to 0 before the
Rev. 5.00 Jan 06, 2006 page 402 of 818
REJ09B0273-0500
and FER bits of the SSR to identify the error. After executing the necessary error handling,
clear ORER, PER, and FER all to 0. Receiving cannot resume if ORER, PER or FER remain
set to 1. When a framing error occurs, the RxD pin can be read to detect the break state.
is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0.
The RxI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1.
stop bit of the current frame is received. If the DMAC is started by a receive-data-full interrupt
(RxI) to read RDR, the RDRF bit is cleared automatically so this step is unnecessary.
TDRE
TEND
Serial
Example: 8-bit data with parity and one stop bit
data
interrupt
request
1
TxI
Start
Figure 13.6 SCI Transmit Operation in Asynchronous Mode
bit
0
handler writes
data in TDR
TxI interrupt
TDRE to 0
and clears
D0 D1
1 frame
Data
D7
Parity
bit
0/1
request
TxI
Stop
bit
1
Start
bit
0
D0
D1
Data
D7 0/1
TEI interrupt request
Parity
bit
Stop
bit
1
(marking
state)
Idle
1