HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 554

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 17 I/O Ports (I/O)
17.8.2
The port G data register (PGDR) is a 16-bit readable/writable register that stores port G data. Bits
PG15DR to PG0DR correspond to pins PG15/TIOB5/IRQ5 to PG0/ADTRG/IRQOUT.
When a pin functions as a general output, if a value is written to PGDR, that value is output
directly from the pin, and if PGDR is read, the register value is returned directly regardless of the
pin state.
When a pin functions as a general input, if PGDR is read the pin state, not the register value, is
returned directly. If a value is written to PGDR, although that value is written into PGDR it does
not affect the pin state. Table 17.14 summarizes port G data register read/write operations.
PGDR is initialized by a power-on reset (excluding a WDT power-on reset), and in hardware
standby mode. It is not initialized in software standby mode or sleep mode.
Table 17.14 Port G Data Register (PGDR) Read/Write Operations
PGIOR
0
1
Rev. 5.00 Jan 06, 2006 page 532 of 818
REJ09B0273-0500
Initial value:
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Port G Data Register (PGDR)
Pin Function
General input
Other than general
input
General output
Other than general
output
PG15
15
DR
0
PG14
14
DR
0
PG13
13
DR
0
PG12
12
DR
0
Read
Pin state
Pin state
PGDR value
PGDR value
PG11
11
DR
0
PG10
10
DR
0
PG9
DR
9
0
Write
Value is written to PGDR, but does not affect
pin state
Value is written to PGDR, but does not affect
pin state
Write value is output from pin
Value is written to PGDR, but does not affect
pin state
PG8
DR
8
0
PG7
DR
7
0
PG6
DR
6
0
PG5
DR
5
0
PG4
DR
4
0
PG3
DR
3
0
PG2
DR
2
0
PG1
DR
1
0
PG0
DR
0
0