HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 540

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 17 I/O Ports (I/O)
17.2.1
The port A register is shown in table 17.1.
Table 17.1 Port A Register
Name
Port A data register
Note: A register access is performed in two cycles regardless of the access size.
17.2.2
The port A data register (PADR) is a 16-bit readable/writable register that stores port A data. Bits
PA15DR to PA0DR correspond to pins PA15/A15 to PA0/A0.
When a pin functions as a general output, if a value is written to PADR, that value is output
directly from the pin, and if PADR is read, the register value is returned directly regardless of the
pin state. When the POD pin is driven low, general outputs go to the high-impedance state
regardless of the PADR value. When the POD pin is driven high, the written value is output from
the pin.
When a pin functions as a general input, if PADR is read the pin state, not the register value, is
returned directly. If a value is written to PADR, although that value is written into PADR it does
not affect the pin state. Table 17.2 summarizes port A data register read/write operations.
PADR is initialized by a power-on reset (excluding a WDT power-on reset), and in hardware
standby mode. It is not initialized in software standby mode or sleep mode.
Rev. 5.00 Jan 06, 2006 page 518 of 818
REJ09B0273-0500
Initial value:
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Register Configuration
Port A Data Register (PADR)
PA15
DR
15
0
PA14
DR
14
0
PA13
DR
13
0
Abbreviation
PADR
PA12
DR
12
0
PA11
DR
11
0
PA10
DR
10
0
R/W
R/W
PA9
DR
9
0
PA8
DR
8
0
Initial Value
H'0000
PA7
DR
7
0
PA6
DR
6
0
PA5
DR
5
0
Address
H'FFFF8380
PA4
DR
4
0
PA3
DR
3
0
PA2
DR
2
0
Access Size
8, 16
PA1
DR
1
0
PA0
DR
0
0