HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 183

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Direct Address Transfer Mode: Data is read from the transfer source during the data read cycle,
and written to the transfer destination during the write cycle, so transfer is conducted in two bus
cycles. At this time, the transfer data is temporarily stored in the DMAC. With the kind of external
memory transfer shown in figure 9.7, data is read from one of the memories by the DMAC during
a read cycle, then written to the other external memory during the subsequent write cycle. Figure
9.8 shows the timing for this operation.
1st bus cycle
2nd bus cycle
The SAR value is taken as the address, and data is read from the transfer source
module and stored temporarily in the DMAC.
The DAR value is taken as the address, and data stored in the DMAC's data
buffer is written to the transfer destination module.
Figure 9.7 Direct Address Operation during Dual Address Mode
Data buffer
Data buffer
DMAC
DMAC
SAR
DAR
SAR
DAR
2nd bus cycle
1st bus cycle
Section 9 Direct Memory Access Controller (DMAC)
Transfer destination
Transfer destination
Rev. 5.00 Jan 06, 2006 page 161 of 818
Transfer source
Transfer source
Memory
Memory
module
module
module
module
REJ09B0273-0500