HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 432

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 13 Serial Communication Interface (SCI)
Receiving Multiprocessor Serial Data: Figure 13.13 shows a sample flowchart for receiving
multiprocessor serial data. The procedure for receiving multiprocessor serial data is listed below.
1. SCI initialization: Set the RxD pin using the PFC.
2. ID receive cycle: Set the MPIE bit in the serial control register (SCR) to 1.
3. SCI status check and compare to ID reception: Read the serial status register (SSR), check that
4. Receive error handling and break detection: If a receive error occurs, read the ORER and FER
5. SCI status check and data receiving: Read SSR, check that RDRF is set to 1, then read data
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RDRF is set to 1, then read data from the receive data register (RDR) and compare with the
processor’s own ID. If the ID does not match the receive data, set MPIE to 1 again and clear
RDRF to 0. If the ID matches the receive data, clear RDRF to 0.
bits in SSR to identify the error. After executing the necessary error processing, clear both
ORER and FER to 0. Receiving cannot resume if ORER or FER remain set to 1. When a
framing error occurs, the RxD pin can be read to detect the break state.
from the receive data register (RDR).
TDRE
TEND
Example: 8-bit data with multiprocessor bit and one stop bit
Serial
data
interrupt
request
1
TxI
Start
bit
0
clears TDRE to 0
data in TDR and
Figure 13.12 SCI Multiprocessor Transmit Operation
handler writes
TxI interrupt
D0 D1
1 frame
Data
Multiprocessor
D7
0/1
interrupt
bit
request
TxI
Stop
bit
1
Start
bit
0
D0
D1
Data
Multiprocessor
D7 0/1
bit
interrupt
request
TEI
Stop
bit
1
(marking
state)
Idle
1