HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 664

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 21 Power-Down State
Table 21.1 Power-Down State Conditions
Mode
Hardware
standby
Software
standby
Sleep
Notes: 1. SBYCR: standby control register. SBY: standby bit
Rev. 5.00 Jan 06, 2006 page 642 of 818
REJ09B0273-0500
2. Some bits within on-chip peripheral module registers are initialized by the standby
3. The status of the I/O port in standby mode is set by the port high impedance bit (HIZ) of
Entering
Procedure
Low-level
input at
HSTBY pin
Execute
SLEEP
instruction
with SBY bit
set to 1 in
SBYCR
Execute
SLEEP
instruction
with SBY bit
set to 0 in
SBYCR
mode; some are not. Refer to table 21.3, Register States in the Standby Mode, in
section 21.4.1, Transition to Standby Mode. Also refer to the register descriptions for
each peripheral module.
the SBYCR. Refer to section 21.2, Standby Control Register (SBYCR). For pin status
other than for the I/O port, refer to Appendix B, Pin States.
Clock CPU
Halted Halted Halted
Halt
Run
Halt
Halt
CPU
Registers
Held
Held
State
On-Chip
Peripheral
Modules
Undefined Held *
Halt *
Run
1
RAM
Held
Held
2
I/O
Ports
Initialized High-level
Held or
high
impe-
dance *
Held
3
Canceling
Procedure
input at
HSTBY pin,
executing
power-on
reset
• NMI
• Power-on
• Interrupt
• DMAC
• Power-on
interrupt
reset
address
error
reset