AD6652BC/PCB Analog Devices Inc, AD6652BC/PCB Datasheet - Page 13

• Manufacturer Part Number: AD6652BC/PCB
• Description: BOARD EVAL W/AD6652 & SOFTWARE
• Manufacturer: Analog Devices Inc

Specifications of AD6652BC/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6652
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pin No.
DDC OUTPUTS
PARALLEL OUTPUT PORT CONTROL
MICROPORT CONTROL
1
2
3
4
5
PDWN pins must be the same logic level: both logic high or both logic low.
PACH0 and PACH1 form a 2-bit output word in the parallel output mode that identifies the processing channel (0, 1, 2, or 3) whose data appears on Port A parallel
outputs. Likewise, PBCH0 and PBCH1 identify the channel for Port B.
Pins with a pull-down resistor of nominal 70 kΩ.
Mode 0 is Intel nonmultiplexed (IMN), and Mode 1 is Motorola nonmultiplexed (MNM). Pin logic level corresponds to mode.
Pins with a pull-up resistor of nominal 70 kΩ.
B11
C11
C12
P8
B3
R2
F1, D1, D2,
C2, B2, E2,
A4, A2
P2, R3, N3,
M2, M3, T3,
L1, L2
E1, C1, F3,
G2, G1, G3,
H3, H2
P3, R4, P4,
T4, R5, T5,
P5, R6
N1
R1
K2
H1
P7
T6
C5, A5, C6,
A6, B7, C7,
B8, C8
B4, C3, A3
C4
C9
B6
A9
A7
Mnemonic
LIA
LIA
LIB
LIB
PACH0_LACLKOUT
PACH0_LBCLKOUT
PA[7:0]_LA[7:0]
PB[7:0_LB[7:0]
PA[15:8]
PB[15:8]
PAIQ
PBIQ
PAACK
PAREQ
PBACK
PBREQ
D[7:0]
A[2:0]
DS(RD)
DTACK(RDY)
R/W (WR)
MODE
CS
3
4
4
4
4, 5
2
2
Type
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Output
Input
Output
I/O
Input
Input
Output
Input
Input
Input
Function
Level Indicator, Input A, Data A.
Level Indicator, Input A, Data A.
Level Indicator, Input B, Data B.
Level Indicator, Input B, Data B.
Channel ID Output Bit, LSB, for Parallel Port A, or Link Port A Clock Output.
Function depends on logic state of 0x1B:7 of output port control register.
Channel ID Output Bit, LSB, for Parallel Port B, or Link Port B Clock Output.
Function depends on logic state of 0x1D:7 of output port control register.
Link Port A Data or Parallel Port A Data [7:0], Eight Pins.
Link Port B Data or Parallel Port B Data [7:0], Eight Pins.
Parallel Port A Data [15:8], Eight Pins.
Parallel Port B Data [15:8], Eight Pins.
Parallel Port A I or Q Data Indicator, I = High, Q = Low.
Parallel Port B I or Q Data Indicator, I = High, Q = Low.
Parallel Port A Acknowledge.
Parallel Port A Request.
Parallel Port B Acknowledge.
Parallel Port B Request.
Bidirectional Microport Data, Eight Pins. This bus is three-stated when CS is high.
Microport Address Bus, 3 Pins.
Function depends upon MODE pin.
Active Low Data Strobe when MODE = 1.
Active Low Read Strobe when MODE = 0.
Function depends upon MODE pin.
Active Low Data Acknowledge when MODE = 1.
Microport Status Pin when MODE = 0.
Read/Write Strobe when MODE = 1. Active Low Write strobe when MODE = 0.
Mode Select Pin. 0 = Intel mode, 1 = Motorola mode.
Active Low Chip Select. Logic 1 three-states the microport data bus.
Rev. 0 | Page 13 of 76
AD6652