AD6652BC/PCB Analog Devices Inc, AD6652BC/PCB Datasheet - Page 68

• Manufacturer Part Number: AD6652BC/PCB
• Description: BOARD EVAL W/AD6652 & SOFTWARE
• Manufacturer: Analog Devices Inc

Specifications of AD6652BC/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6652
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD6652
Address
1E
1
2
0x0E: AGC A Loop Gain
This 8-bit register defines the open loop gain K. Its value can be
set from 0 to 0.996 in steps of 0.0039. This value of K is updated
in the AGC loop each time the AGC is initialized.
0x0F: AGC A Pole Location
This 8-bit register defines the open loop filter pole location P. Its
value can be set from
P is updated in the AGC loop each time the AGC is initialized.
This open loop pole location directly impacts the closed loop
pole locations. See the Automatic Gain Control section.
0x10: AGC A Average Samples
This 6-bit register contains the scale used for the CIC filter and
the number of power samples to be averaged before being fed t
the CIC filter.
Bits 5–2 define the scale used for the CIC filter.
Bits 1–0 define the n
they are sent to the C
set between 1 and 4 with 00 meaning one sample and 11 m
ing four samples.
0x11: AGC A Update Decimation
This 12-bit register sets the AGC decimation ratio from 1 t
4096. Set an appropriate scaling factor to avoid loss of bits.
0x12: AGC B Control Register
Bits 7–5 define the o
word can be 4 to 8, 10, 12, or 16 bits wide. The control register
bit representation to obtain different output word lengths is
given in Table 29.
Bit 4 of this register sets the mode of operation for the AGC.
When this bit is 0, the AGC tracks to maintain the output signal
level; when this bit is 1, the AGC tracks to maintain a constant
clipping error. See the Automatic Gain Control section for
details about these two modes.
Bits 3–1 are used to configure the synchronization of the AGC.
Set the LHB A and/or LHB B enable bits to logic low only when the entire block functions
shut down.
PCLK boots as a slave.
Register
Port Clock Control
umber of samples to be averaged before
utput word length of the AGC. The output
IC decimating filter. This number can be
0 to 0.996 in steps of 0.0039. This value of
Bit Width
3
o
ean-
Comments
1:
0:
2–1:
0:
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o
Channel data interleaved
1:
0:
AGC_CH select
1:
0:
PCLK divisor
PCLK master/slave
0:
1:
The CIC decimator filter in the AGC can be indirectly
synchronized to an externally generated signal. When synchro-
nized, the AGC outputs an update sample for the AGC error
calculation and filtering. This way, the AGC gain changes can be
synchronized to a Rake receiver or other external block.
Note: The hold-off counter of AGC B shares the pin sync
assigned to DDC processing Channel 2. There
intends to use the AGC B’s hold-off counter, the user must
attach the external sync signal to the pin sync that will be
assigned to DDC Channel 2. The hold-off counter must be
programmed with a 16-bit number that corresponds to the
desired delay before a new CIC decimated value is updated.
Writing a logic high to the proper pin sync pin triggers the AGC
hold-off counter with a retriggerable one-shot pulse every time
the pin is written high.
Bit 3 is the sync now bit. If the user chooses not to use pin sync
signals, the user can use the Sync Now command by program-
ming this bit high. This performs an immediate start of
decimation for a new update sample and initializes the AGC, if
Bit 2 is set. This bit has a one-shot characteristic and does
need to be reset in order to respond to a new logic high being
written to it. Use of the sync now bit bypasses the AGC hold-off
counters; therefore, the name Sync Now.
Bit 2 is used to determine whether the AGC should initia
a Sync Now or not. When this bit is set, the CIC filter is cleared
and new values for CIC decimation, number of averaging
samples, CIC scale, signal gain Gs,
are loaded. When Bit 2 = 0, the above-mentioned parameters are
not updated and the CIC filter is not cleared. In both cases, an
AGC update sample is output from the CIC filter and the
decimator starts operating towards the next output sample
whenever a Sync Now occurs.
Bit 1 is used to ignore repetitive Pin_Sync signals. In some
applications, the synchronization signal might occur periodi-
cally. If this bit is clear, each Pin_Sync resynchronizes the AGC.
(LHB signal interleaving, LHB filtering, and AGC
2-channel mode/separate AB
4-channel mode/AB same port
Data comes from AGCs
Data comes from channels
Slave
Master
2
gain K, and pole parameter P
functions) are to be
fore, if the user
lize on
not