AD6652BC/PCB Analog Devices Inc, AD6652BC/PCB Datasheet - Page 28

• Manufacturer Part Number: AD6652BC/PCB
• Description: BOARD EVAL W/AD6652 & SOFTWARE
• Manufacturer: Analog Devices Inc

Specifications of AD6652BC/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6652
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD6652
Clock Input Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result can be sensiti
to ACLK clock duty cycle. Commonly a 5% tolerance is
required on the clock duty cycle to maintain dynamic perform-
ance characteristics. The AD6652 contains a clock duty cycle
stabilizer that re-times the nonsampling edge, providing a
internal clock signal
sta ilizing is engaged by setting DUTYEN to logic high. This
allo s a wide range of ACLK clock input duty cycles without
affec
Th duty cycle stabilizer uses a delay-locked loop (DLL) to
crea
sam
the
Hi
the c
inpu
calculated with the following equation:
In the equation, the rms aperture jitter, t , represents the root-
sum square of all jitter sources, which include the clock inpu
analog input signal, and ADC aperture jitter specification.
Undersampling applications are particularly sensitive to jitter.
To minimize clock jitter, treat the ACLK clock input as an
analog signal. Power supplies for clock drivers should be
separated from the ADC output driver supplies to avoid
gh
b
e
w
DLL to ac
te the nonsampling edge. As a result, any changes to the
pling frequency require approximately 2 ms to 3 ms to al
t frequency (
ting the performance of the AD6652 ADC stage.
lock input. The degradation in SNR at a given full-scale
SNR degradation = 20 × log10 [1/2 × p × f
speed, high resolution ADCs are sensitive to the quality of
quire and lock to the new rate.
f
INPUT
with a nominal 50% duty cycle. Duty cycle
) due only to aperture jitter (t
A
INPUT
× t
A
) can be
A
]
n
t,
Rev. 0 | Page 28 of 76
low
ve
modulating the clock
crystal-controlled osci
ACLK clock is generated from another type of source (by
gating, dividing, or other methods), re-time it by the origi
clock at the
ADC Power-Down Mode
Th
tio
bo
a p
Lo
shu
bo
tog
Fo
sh
typ
inp
co
ADC Wake-Up Time
The deco
when entering standby mo
returning to normal operation. As a result, the wake-up time is
related to the time spent in standby mode. Shorter standby
cycles result in proportionally shorter wake-up times. With
recommended 0.1 µF and 10 µF deco
and
referenc
operatio
ould remain st
nsumption for
th PDWN pin
th ADC chann . Both power-
r maximum p
nal to its samp g rate. Norma
w power dissi
e power dissip
ower-down m e by setting bo
ether either h
ical power co
uts remain ac
tting down th eference buffers and biasing ne
REFB, it takes approximately 1 s to full
e buffer decoupling capacitors, and 5 ms to restore full
n.
upling capacitors on REFT and REFB are discharged
last s
pat
ow
nsum
s b
igh
atic
tive
tep.
od
e r
ate
lin
els
th
er savings, the
e set to logic lo
ion in power-d
e ADC is 12 mW
d by the AD6652 front-end AD is propor-
or low for pro r ADC operat
while in stan
while in stan
signal with digital noise. Low jitter,
ption of 1 m
llators make the best clock sources. If the
de, and then must be recharged when
down
l A
dby
dby
AC
th
w. T
ow
pe
W
.
DC operation
PDWN pins t
LK and analo
upling capacitors on REFT
n mode is ach
for the ADC.
mode, result
mode, typical power
he ADC can
pins must b
y discharge the
ion
ing
o lo
two
g in
req
If t
iev
C
be
e d
.
he clock
uires that
placed in
ed by
in a
gic high.
riven
rks of
put(s)
nal
the