AD6652BC/PCB Analog Devices Inc, AD6652BC/PCB Datasheet - Page 53

• Manufacturer Part Number: AD6652BC/PCB
• Description: BOARD EVAL W/AD6652 & SOFTWARE
• Manufacturer: Analog Devices Inc

Specifications of AD6652BC/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6652
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LINK PORT
The AD6652 has two configurable link ports that provide a
seamless data interface with the TigerSHARC TS-101 series
DSP. Each link port allows the AD6652 to write output data to
the receive DMA channel in the TigerSHARC for transfer to
memory. Because they operate independently o
each link port can be connected to a different TigerSHARC or
different link ports on the same TigerSHARC. Figure 59 sh
how to connect one of the two AD6652 link ports to one of the
four TigerSHARC link ports. Link Port A is configured thro
Register 0x1B and Link Port B is configured through
Register 0x1D.
LINK PORT DATA FORMAT
Each link port can output data to the TigerSHARC in five
different formats: 2-channel, 4-channel, dedicated AGC,
redundant AGC with receive signal strength indicator (RSSI)
word, and redundant AGC without RSSI word. Each format
outputs two bytes of I data and two bytes of Q data to form a
4-byte IQ pair. Because the TigerSHARC link port transfers data
in quad-word (16-byte) blocks, four IQ pairs can make up one
quad-word. If the channel data is selected (Bit 0 = 0 of 0x1B/
0x1D), then 4-byte IQ words of the four channels can be outpu
in succession, or alternating channel pair IQ
output. Figure 60 and Figure 61 show the quad-word trans-
mitted for each case with corresponding register values for
configuring each link port.
LINK PORT A
LINK PO
If AGC o
be sen
config
outpu
ting th
IQ wo
two bytes (12 bits appended with 4 0s), so the link port sends
two bytes of 0s immediately after each RSSI wor
16-byte quad-word.
LINK PORT
A OR B
Figure 59. Link Port Connection between AD6652 and TigerSHARC
t data fro
RT B
t with th
rds (Bit 2
ured to o
e same d
utput
AD6652
(4 BYTES)
(4
(4
CH 0 I, Q
C
C
e IQ pair from each AGC. Each link port can be
H 0 I, Q
H 2 I, Q
m the same AGC. If both link ports are transmit-
BYTES)
BYTES)
is selected (Bit 0 = 1), then RSSI information can
LCLKOUT
ata, then RSSI information must be sent with the
utput data from one AGC, or both link ports can
= 0). Note that the actual RSSI word is only
LCLKIN
PCLK
Figure 60. Link Port Data fr
LDAT
ADDR 0x1B OR 0x1D BIT 0 =
ADDR 0x1B AND 0x1D BIT 0 = 0, BIT 1 = 1
(4 BYTES)
(4
(4 BYTES)
CH 1 I, Q
CH 1 I, Q
CH 3 I, Q
BYTES)
8
(4 BYTES)
(4 BYTES)
(4 BYTES)
CH 2 I, Q
CH 0 I, Q
CH 2 I, Q
LCLKIN
LCLKOUT
LDAT
TigerSHARC
PCLK
om RCF
0, BIT 1 = 0
words can be
f each other,
d to make a full
(4 BYTES)
(4 BYTES)
(4 BYTES
CH 3 I, Q
CH 1 I, Q
CH 3 I
, Q
)
ows
ugh
Rev. 0 | Page 53 of 76
t
Note that Bit 0 = 1, Bit 1 = 0, and Bit 2 = 1 is not a valid
configuration. Bit 2 must be set to 0, to output AGC A IQ and
RSSI words on Link Port A and AGC B IQ and RSSI words on
Link Port B.
LINK PORT A
LINK PORT B
LINK PORT TIMING
Both link ports run off of PCLK, which can be externally
provided to the chip (Address 0x1E Bit 0 = 0) or generated from
the master clock of the AD6652 (Address 0x1E Bit 0 = 1). This
register boots to 0 (slave mode) and allows the user to control
the data rate comi
as 100 MHz in slave mode.
The link port provides 1-byte data words (LA[7:0], LB[7:0]
pins) and output clocks (LACLKOUT, LBCLKOUT pins) in
response to a ready signal (LACLKIN, LBCLKIN pins) from the
receiver. Each link port transmits 8 bits on each edge of
LCLKOUT, requiring 8 LCLKOUT cycles to comp
transmission of the full 16 bytes of a TigerSHARC quad-word.
Due to the TigerSHARC link port protocol, the AD6652 mu
wait at least 6 PCLK cycles after the TigerSHARC is ready t
receive data, as indicated by the TigerSHARC setting t
respective AD6652 LCLKIN pin high. Once the AD6652 link
port has waited the appropriate number of PCLK cycles a
begun transmitting data, the TigerSHARC does a connectivity
check by sending the AD6652 LCLKIN low and then high while
the data is being transmitted. This tells the AD6652 link port
that the TigerSHARC’s DMA is ready to receive the next quad-
word after completion of the current quad-word. Because t
connectivity check is done in parallel to the data transmission,
the AD6652 can stream uninterrupted data to the TigerSHA
LCLKOUT
LDAT[7:0]
LINK PORT
LINK PORT
LCLKIN
A OR B
A OR B
TigerSHARC READY TO
RECEIVE QUAD-WORD
AGC A I, Q
AGC A I, Q
AGC A I, Q
AGC B I, Q
(4 BYTES)
(4 BYTES)
(4 BYTES)
(4 BYTES)
WAIT ≥ 6 CYCLES
Figure 61. Link Port Data from AGC
ng from the AD6652. PCLK can be run as fast
ADDR 0x1B OR 0x1D BIT 0 = 1, BIT 1 = 0, BIT 2 = 0
ADDR 0x1B OR 0x1D BIT 0 = 1, BIT 1 = 0, BIT 2 = 1
ADDR 0x1B AND 0x1D BIT 0 = 1, BIT 1 = 1, BIT 2 = 0
Figure 62. Link Port Data Transfer
AGC A RSSI
AGC B RSSI
AGC A RSSI
AGC B I, Q
(4 BYTES)
(4 BYTES)
(4 BYTES)
(4 BYTES)
D0 D1 D2 D3 D4
AGC A I, Q
AGC B I
AGC A I, Q
AGC B I, Q
(4 BYTES)
(4 BYTES)
(4 BYTES)
(4 BYTES)
RECEIVE NEXT QUAD-WORD
, Q
TigerSHARC READY TO
AGC B RSSI
D15 D0 D1 D2
AGC B RSSI
NEXT QUAD-WORD
AGC A RSSI
AGC B I, Q
(4 BYTES)
(4 BYTES)
(4 BYTES)
(4 BYTES)
lete
AD6652
he
nd has
he
o
st
RC.