AD6652BC/PCB Analog Devices Inc, AD6652BC/PCB Datasheet - Page 56

• Manufacturer Part Number: AD6652BC/PCB
• Description: BOARD EVAL W/AD6652 & SOFTWARE
• Manufacturer: Analog Devices Inc

Specifications of AD6652BC/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6652
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD6652
ACCESS CONTROL REGISTER (ACR)
External Address 7
The ACR specifies certain programming characteristics such as
autoincrement or broadcast, which are to be applied to the
incoming instructions, and selects which channel(s) are to be
programmed by th
Bit 7 of this register is the autoincrement bit. If this bit is a 1
then the CAR register, described in the Channel Address
Register (CAR) section, increments its value after every access
to the channel. This allows blocks of address space such as
coefficient memory to be initialized more efficiently.
B
Bits 5–2 are interpreted. If broadcast is 0 the
are referred to as instruction bits (Instructio
compared with the
matche
allo
mem
sa
If
m
sim
10 p
for
a sin
The
care
s
in
desir
B
fo
a
in
A[9:8]
Table 23. Microport
Inst
0000
0001
0010
0100
1000
1001
1100
1101
1110
1111
1
et hig
n access to multiple c nnels, then these bits are ignored. If the
A[9:8] bits control which c
it 6 of the register is the broadcast bit, which determines how
its 1–0 of the ACR ar address bits that decode which of the
me serial port of a h t processor to configure up to 16 chips.
ultiple AD6652 chan els and/or chips to be configured
ternal bus contentio
ur channels are bein
struction decodes an ccess to a subset of chips, then the
the broadcast bit is h h, the Instruction[3:0] word allows
ultaneously indepe
smart antenna syst
ws up to 16 chips t
s” in the digital de
ruction
ossible instruction
x’s in the commen
gle antenna or car
ed, the broadcast t should be set low.
ory mapped with
h) readback is n
bits otherwise d
s the CHIP_ID
All chips and all
Channe 0, 1, 2 of all chips have access.
Channe
All chips get the access.
All chip
All chip
All chip
All chip
All chip
All chip
Comm
e microport or serial port.
CH
Instructions,
n. Th
coding. When broadcas
ent
o be connected to
os
ems, where multiple channe
bi
g acces
[3:0] pins determines the acce
out external logic. This also
e
ha
hannel is decoded for access
ndent of the CHIP_ID[
rier can be configured simu
ot valid b
n
s are defined in Table 23. This is us
t portion of the table repres
s with Chip_ID[3:0] =
s with Chip_ID[3:0] = x
s with Chip_
s with Chip
s with Ch
s with Chip_ID[3:0] =
etermine
ls
ls 1, 2, 3 of all chi
IP_ID[3:0
ig
a
erefore, if readback is subsequently
sed. If the instruction bits decode
channe
ip_ID[3:0] = xx10 have access.
ecause of the p
the channel being accessed.
] pins. The instruction that
_ID[3:0] = xx01 have access.
ID[3:0] = xx00 have access.
7:5–2
ls have access.
1
ps have access.
the same port and
xxx0 have access.
xx11 have access.
n Bits 5–2, which
n[3:0]), are
xx1 have access.
t is enabled (Bit 6
.
3:0] pins. The
otential for
ls listening to
ent “don’t
allows the
ltaneously.
ss. This
eful
,
Rev. 0 | Page 56 of 76
1
1
1
1
1
1
CHANNEL ADDRESS REGISTER (CAR)
External Address 6
The user writes the 8-bit internal address o
to be programmed in the CAR. If the
ACR is 1, then this value is incremented after every access to
DR0 register, which in turn accesses the location pointed to
this address. The channel address register cannot be read back
while the broadcast bit is set high.
SOFT_SYNC CONTROL REGISTER
External Address 5
The SOFT_SYNC control register is write only. The regist
name is somewhat deceiving in that this re
BIST (built-in self-test) commands that turn internal test
signals off or on, namely, pseudonoise and negative full-scale
sin
Bits 0–3
for each
or all of
recipien
signal is
below. A
signal, if
Bit 4 is t
logic hig
hold-of
Bits 3–0
for furth
Channel
Bit 5 is t
logic hig
frequen
accordin
Synchro
the Cha
Bit 6 co
this bit is lo
connect
this is n
internal
purpose
choice.
register.
If Bit 7
made av
the inte al pseudorandom noise generator is enabled and this
data is a
function
conjunc
in-syste
e wav
The internal test signals are configur
is logic l
f counter of the sele
nfigures ho
rn
cy h
m chip
nnel
orma
ts of
ed to
vailable to
tion with th
he start software synchronizi
he h
niza
s and
thes
ailable to the internal data bus. I
e, at Bits 7 an
test si
of this register are the
of t
gen
h initiates a one-sh
above. See the Cha
er in
h init
s of B
g to
pin-sy
des
Addres
w, then
old-o
he fou
erated
ired.
e bits
op so
tion s
Addr
a sof
form
Bits
l ope
the
iate
this
gna
its 6 and 7 facilitate BIST functions. Also, in
testing.
nc
ow
s Reg
ff counter of the selected DDC cha
DDC NCOs according to the
3–0 above. See the C
t_sync sy
s a one-shot-type pulse to trigger the
ftware synchronizing pulse. Writing t
ls are connected to a
ection. Progra
ess Register 0x82 of each channel.
ration. If this bit is logic high
simply
ation. Programming this b
r DDC channels. Writing a logic hig
signal can
overrides any NCO
, a negative full-scale sig
w the internal input data bus is configured. If
the internal input data bus. The combined
by Bits 4 and 5 o
the ADCs (analog–to-digital converters) are
e MISR registers, this allows for detailed
d 6, explained below.
ister 0x82 of each channel.
selects the indicated channel(s) to be
nchronizing pulse—whenever such
cted DDC channels according to
nnel/Chip Synchronization section
ot-type pulse to trigger the start
be used in addition to a soft-sync
SOFT_SYNC channel enable bits
mming this bit also programs
f this register as described
ng pulse. Writing this bit to
autoincrement bit of the
hannel/Chip
ll DDC NCOs for BIST
programmed input
f this bit is high, then
nal is generated and
gister also contains
f a channel register
ed in Bit 7 of this
it also programs
, then the
user’s choice—
nnels
h to one
his bit to
hop
er
by
the