AD6652BC/PCB Analog Devices Inc, AD6652BC/PCB Datasheet - Page 25

• Manufacturer Part Number: AD6652BC/PCB
• Description: BOARD EVAL W/AD6652 & SOFTWARE
• Manufacturer: Analog Devices Inc

Specifications of AD6652BC/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6652
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

For best dynamic performance, th
the differential analog inputs should be matched such that
common-mode settling errors are symmetrical. These errors are
reduced by the common-mode rejection of the ADC.
The SHA should be driven from a source that keeps the signal
peak
voltage.
levels are defined as follows:
The minimum common-mode input level allows the AD66
accommodate ground-referenced inputs.
Although optimum performance is achieved with a differ
in
I
opposite input should be set to midscale by connecting it to an
appropriate reference. For example, a 2 V p-p signal can be
applied to VIN+, while a 1 V reference is applied to VIN−. The
AD6652 then accepts a signal varying between 2 V and 0 V. In
the single-ended configuration, distortion performance might
degrade significantly, compared to the differential case.
However, the effect is less noticeable at lower analog input
frequencies.
Differential Input Configurations
Optimum performance is achieved while driving the AD6652
inputs in a differential input configuration. For baseband
applications to Nyquist, the AD8138 Differential Driver
provides excellent performance and a flexible interface to the
ADC The output common-mode voltage of the AD8138 is
easily set to one-half of AVDD, and the driver can be configured
in a Sallen-Key filter topology to provide band limiting of the
input signal.
At input frequencies above Nyquist, the performance of most
amplifiers is not adequate to achieve the true performance of
the AD6652 ADC stage.
n this configuration, one input accepts the signal, while the
put, a single-ended source can be driven into VIN+ or VIN−.
VINA–
VINA+
s within the allowable range for the selected referenc
VCM
VCM
Figure 38. Switched-Capacitor SHA Input for One ADC Channel
The minimum and maximum common- ode in
MIN
MAX
= VREF/2
= (AVDD + VREF)/2
S
S
S = SAMPLE
H = HOLD
5pF
5pF
e source impedances driving
S
S
m
H
H
put
e
ential
52 to
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This is especially true in IF undersampling applications in
which input frequencies in the range of 70 MHz to 200 MHz are
being sampled. For these applications, differential transform
coupling is the recommended input configuration, as shown i
Figure 39. Transforme
ratio broadband RF transfor
be considered when selecting a transformer. Most RF
transformers saturate at frequencies below a few MHz, and
excessive signal power can also cause core saturation, which
leads to distortion.
ADC Voltage Reference
A stable and accurate 0.5 V voltage reference is built into the
AD6652. The input span of the ADC tracks reference voltage
changes linearly. An internal differential reference buffer creates
positive and negative reference voltages, REFT and REFB,
respectively, that define the span of the ADC core. The output
common mode of the reference buffer is set to midsupply, and
the REFT and REFB voltages and span are defined as follows:
As shown by the equations above, the REFT and REFB voltages
are symmetrical about the midsupply voltage and, by definition,
the input span is twice the value of the VREF voltage. Proper
operation of the AD6652 requires that VREF be no less than
0.5 V and no greater than 1.0 V.
The internal voltage reference can be pin-strapped to fixed
values of 0.5 V or 1.0 V, or adjusted within the same range, as
discussed in the Internal Reference Connection section. Maxi-
mum SNR performance is achieved with the reference set to the
largest input span of 2 V p-p. The relative SNR degradation is
3 dB when changing from 2 V p-p mode to 1 V p-p mode.
If operation using an external reference voltage is desired, it can
be substituted for the internal reference, as detailed in the
External Reference Operation section.
Figure 39. Differential AC-
REFT =
REFB = 1/2 (AVDD − VREF)
Span = 2 × (REFT − REFB) = 2 × VREF
1V p-p
1/2 (AVDD + VREF)
49.9Ω
r T1 is a center-tapped, 1:4 impedance
Coupled Input for One Channel of the AD6652
0.1µF
T1
mer. The signal characteristics must
1kΩ
1kΩ
10pF
10pF
50Ω
50
Ω
VINA
VINB
AD6652
AVDD
AGND
AD6652
er
n