AD6652BC/PCB Analog Devices Inc, AD6652BC/PCB Datasheet - Page 51

• Manufacturer Part Number: AD6652BC/PCB
• Description: BOARD EVAL W/AD6652 & SOFTWARE
• Manufacturer: Analog Devices Inc

Specifications of AD6652BC/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6652
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PxCH[1:0]
The 8-bit concurrent format provides 8 bits of I data and 8 bits
of Q data simultaneously during one PCLK cycle, also triggered
on the rising edge of PCLK. The I byte occupies the most
significant byte of the port, while the Q byte occupies the least
sig
se
channels is output consecutively, the PAIQ and PBIQ output
indicator pins remain high until data from all channels has been
output.
PxCH[1:0]
The PACH[1:0] and PBCH[1:0] pins provide a 2-bit binary
value indicating the source channel of the data currently being
output.
Care should be taken to read data from the port as soon as
possible. If not, the sample will be overwritten when the next
new data sample arrives. This occurs on a per-channel basis;
that is, a Channel 0 sample is overwritten only by a new
Channel 0 sample, and so on.
The order of data output is dependent on when data arrived at
the port, which is a function of total decimation rate, start hold-
off values, and so on. Priority order is, from highest to lowest,
Channels 0, 1, 2, and 3.
Px[15:0]
Px[15:0]
PxACK
PxREQ
t high during the PCLK cycle. Note that if data from multiple
PCLKn
PxACK
PxREQ
PCLKn
nificant byte. The PAIQ and PBIQ output indicator pins are
PxIQ
PxIQ
Figure 56. Channel Mode 8I/8Q Parallel Format
Figure 55. Channel Mode Interleaved Format
t
DPREQ
t
DPIQ
t
DPREQ
t
t
DPCH
DPP
I[15:0]
t
t
DPP
DPIQ
PxCH[1:0] =
Channel #
t
DPCH
PxCH[1:0] =
I[15:8]
Q[7:0]
Channel #
Q[15:0]
Rev. 0 | Page 51 of 76
AGC MODE
Parallel port channel mode is selected by clearing Bit 0 of
Addresses 0x1A and 0x1C for Parallel Ports A and B, respec-
tively. I and Q data output in AGC mode are output from the
AGC, not the individual chann
Channel 0 to Channel 3, while AGC B accepts data from
Channel 2 and Channel 3. Each pair of channels is require
be configu
the ch
port ca
Bit 2 o
contro
AGC m
the 16
and AC
output
and PBIQ output indicator pins are high during this cycle, and
are low otherwise. A 16-bit AGC Q word is provided during the
subsequent PCLK cycle. If the AGC gain word has been updated
since the last sample, a 12-bit RSSI word is provided during the
PCLK cycle following the Q word of 12 MSBs of the parallel
port data pins. This RSSI word is the bit-inverse of the signal
gain word used in the gain multiplier of the AGC.
The data provided by the PACH[1:0] and PBCH[1:0] pins in
AGC mode is different than that provided in channel mode. In
AGC mode, PACH[0] and PBCH[0] indicate the AGC source of
the data currently being output (0 = AGC A, 1 = AGC B).
PACH[1] and PBCH[1] indicate whether the current data is an
I/Q word or an AGC RSSI word (0 = I/Q word, 1 = AGC RSSI
word). The two different AGC outputs are shown in Figure 57
and Figure 58.
PxCH[1:0]
Px[15:0]
PCLKn
PxACK
PxREQ
PxIQ
annels is out o
-bit interleave
f Register Add
l the inclusion f data from AGCs A and B, respectively.
n provide da
of a 16-bit AGC I word for one PCLK cycle. The PAIQ
K are asserte
ode provides only one I&Q format, which is similar to
red such t
Figure 57. AGC with No RSSI Word
ta from
d f
d, t
hat the ge
f p
res
t
o
DPREQ
ormat of channel mode. When both REQ
hase (by typically 180°). Each parallel
he next rising edge of PCLK triggers the
ses 0x1A (Port A) and 0x1C (Port B)
either one or both AGCs. Bit 1 and
neration of output samples from
els. AGC A accepts data from
t
t
DPP
DPIQ
t
DPCH
I[15:0]
PxCH[0] = AGC #
PxCH[1] = 0
Q[15:0]
AD6652
d to