AD6652BC/PCB Analog Devices Inc, AD6652BC/PCB Datasheet - Page 59

• Manufacturer Part Number: AD6652BC/PCB
• Description: BOARD EVAL W/AD6652 & SOFTWARE
• Manufacturer: Analog Devices Inc

Specifications of AD6652BC/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6652
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

NCO control register at Channel Address 0x88. When this bit is
low, then the phase accumulator of the NCO is not cleared, but
starts to add the new NCO frequency word to the accumulator
as soon as
accumulator of the NCO is cleared to 0, and the new word is
then accumulated.
0x85: NCO Frequency Register 0
This register represents the 16 LSBs of the NCO frequency
word. These bits are shadowed and are
working register until the channel is either brought out of sleep
mode, or a Soft_SYNC or Pin_SYNC has been issued. In the
latter two cases, the register is updated when the frequency
Table 24. Channel Address
Channel Address
00–7F
80
81
82
83
84
85
86
87
88
89–8F
90
91
92
93
94
95
96
97–9F
A0
A1
A2
A3
the SYNC occurs. If this bit is high, then the phase
Coefficient Memory (CMEM)
CHANNEL SLEEP
Soft_Sync Control Register
Pin_SYNC Control Register
Start Hold-Off Counter
NCO Frequency Hold-Off Counter
NCO Frequency Register 0
NCO Frequency Register 1
NCO Phase Offset Register
NCO Control Register
Unused
rCIC2 Decimation − 1
rCIC2 Interpolation − 1
rCIC2 Scale
Reserved
CIC5 Decimation − 1
CIC5 Scale
Reserved
Unused
RCF Decimation − 1
RCF Decimation Phase
RCF Number of Taps − 1
RCF Coefficient Offset
Register
Memory Map
not updated to the
Rev. 0 | Page 59 of 76
Bit Wid
20
1
2
3
16
16
16
16
16
9
12
9
12
8
8
5
8
8
8
8
8
th
hold-off counter count reach
hold-off counter value is set to a value of 1, then the register is
updated as soon as the shadow is written.
0x86: NCO Frequency Register 1
This register represents the 16 MSBs of the NCO frequency
word. These bits are shadowed and are not updated to the
working register until the channel is either brought out of sleep
mode, or a Soft_SYNC or Pin_SYNC has been issued. In the
latter two cases, the register is updated only when the frequen
hold-off counter count reaches a value of 1. If the frequency
hold-off counter is set to a value of 1, then the register is
updated as soon
Comments
128 x 20-bit memory
0:
1:
0:
2:
1:
0:
Start hold-off value
NCO_FREQ hold-off value
NCO_FREQ[15:0]
NCO_FREQ[31:16]
NCO_PHASE[15:0]
8-7:
6:
5-4:
3:
2:
1:
0:
M
L
11:
10:
9-5:
4-0:
Reserve
M
4-0:
Reserved (must be written low)
M
P
N
CO
rCIC2
RCF
Taps
rCIC2
CIC5
RCF
RCF
− 1
− 1
− 1
− 1
− 1
d (must be written low)
as the shadow is written.
Sleep bit from EXT_ADDRESS 3
Hop
Start
First SYNC only
Hop_En
Start_En
SYNC input select
00 = A, 01 = B, 10 = C, 11 = D
Input port select B or A, 0 = A, 1 = B
Reserved, write both bits logic low
Clear phase accumulator on hop
Amplitude dither
Phase dither
Bypass (A-input -> I-path, B -> Q)
Reserved, write to logic low
Reserved, write to logic low
rCIC2 _QUIET [4
rCIC2_LOUD [4:0]
CIC5_SCALE[4:0]
es a value of 1. If the frequency
:0]
[1:0]
AD6652
cy