AD6652BC/PCB Analog Devices Inc, AD6652BC/PCB Datasheet - Page 52

• Manufacturer Part Number: AD6652BC/PCB
• Description: BOARD EVAL W/AD6652 & SOFTWARE
• Manufacturer: Analog Devices Inc

Specifications of AD6652BC/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6652
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD6652
PxCH[1:0]
MASTER/SL
Th
mo
T
co
I
AD6652 c c
va
divis
maxim
P
s
I
S
asy
100 MH
n master m de, PCLK is an output whose frequency is the
n slave mo e, external circuitry provides the PCLK signal.
elected by setting Bit 0 of Address 0x1E.
Px[15:0]
lave-mode PCLK signals can be either synchronous or
L
he paralle
PCLKn
PxACK
PxREQ
ntentions n the PCLK pin.
lues for PCLK_divisor[2:1] can range from 0 to 3, integer
CK rate in mas
e paralle
nchrono s. The maximum slave-mode PCLK frequency is
de is set
PxIQ
ors of
um c
z.
lo k frequency divided by the PCLK divisor. Because
1,
l ports operate in either master or
l po
d
u
via the port clock control register (Addres
lock rate of the AD6652 is 65 MHz, the hig
o
o
2, 4,or 8, respectively, can be obtained. Because the
AVE PCLK MODES
rts power up in slave mode to avoid possible
ter mode is also 65 MHz. Master m
Figure 58. AGC with RSSI Word
t
DPREQ
t
t
PxCH[0] = AGC #
t
DPP
DPIQ
I[15:0]
DPCH
PxCH[1] = 0
Q[15:0]
PxCH[0] = AGC #
slave mode. The
PxCH[1] = 1
RSSI[11:0]
ode is
s 0x1E).
hest
Rev. 0 | Page 52 of 76
PARALLEL PORT PIN FUNCTIONS
PCLK
Input/output. As an output (master mode), the maximum
frequency is CLK/n, where CLK is the AD6652 clock and n is a
integer divisor 1, 2, 4 or 8. As an input (slave mode), it might be
asynchronous rel
as an input to avoid possible contentions. Other port outputs
ch
REQ
Active high output, synchronous to PCLK. A logic high on this
pin indicate
A lo
shif
PxAC
Active
pin in
this
data
sam
next r
be h
ava
RE
PAIQ, PBIQ
Hig
low
PAC
Th
mo
sou
ind
indica
wor
PA[
Paral
dep
ange on the rising edge of PCLK.
ese pins
Q (see F
ilable, s
de, thes
.
rce cha
icates t
ted out
h when
endent.
d (1).
15:0],
pled o
gic hig
pin wh
eld hig
H[1:0
accor
lel ou
K
hibit
ising
tes w
hig
h asynch
ding to the program
n the fa
he AGC source (0
hifting begin
tput data por
.
s parall
nnel of the curren
h value remains h
], PBCH[1
e pins form a 2-b
PB[15:0]
h continuous
ever I data is pres
en REQ
edge o
igure 55 to F
serve to identify d
hether the current data word
s that data is available to be shifted out of the port.
ative to the AD6652 CLK. This pin powers up
lling edge of PCLK. Data is shifted out on the
f PCLK after PxACK is sampled. PxACK can
el port data shifting. Applying a logic high to
ronous input. Applying a logic low on this
is high causes the parallel port to shift out
:0]
s 1 PCLK cycle after the assertion of
ts. Contents and format are mode-
igure 58).
ly. In this case, when data becomes
it binary number identifying the
igh until all pending data has been
ent on the port output, otherwise
= AGC A, 1 = AGC B), and [1]
t data word. In AGC mode, [0]
ata in both data modes. In channel
med data mode. PxACK is
is I/Q data (0) or a gain
n