AD6652BC/PCB Analog Devices Inc, AD6652BC/PCB Datasheet - Page 24

• Manufacturer Part Number: AD6652BC/PCB
• Description: BOARD EVAL W/AD6652 & SOFTWARE
• Manufacturer: Analog Devices Inc

Specifications of AD6652BC/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6652
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD6652
THEORY OF OPERATIO
The AD6652 has two analog input channels, four digital filter-
ing channels, and two digital output channels. The IF input
signal passes through several stages before it appears at th
output port(s) as a well-filtered, decimated digital baseba
signal:
•
•
•
•
•
•
•
Any stage can be bypassed with the exception of the ADC f
end. Any combination of processing channels can be combined
or interleaved after the R
filtering objectives that are not possible with just one channel.
In the following sections, each st ge is examined to allow the
user to f
The dual ADC design is useful for diversity reception of signals,
where the ADCs are operating identically on the same carrier
but from two separate antennae. The ADCs can also be
operated with independent analog inputs. The user can sample
any fs/2 frequency segment from dc to 100 MHz using
appropriate low-pass or band-pass filtering at the ADC inputs
with little loss in ADC performance. Operation to 200 MHz
analog input is permitted, but at the expense of increased ADC
distortion.
In nondiversity applications, up to four GSM/EDGE-type
carriers can be concurrently processed from the ADC stage.
Wideband signals, such as WCDMA/CDMA2000, require the
power of two AD6652 processing channels per carrier to
adequately remove adjacent channel interference. When
diversity techniques a
can be processed is halv
ment of diversity reception.
Flexi
(D
one output port. Four synch
frequency hop, and AGC functions to be precisely orchestr
with other devices. The NCO’s phase can be set to produce a
known offset relative to another channel or device.
Programming and control of the AD6652 is accomplished using
an 8-bit parallel interface.
DC) stage allows one to four channels to be interleaved onto
12-bit A/D conversio
Frequency translation from IF to baseband using
quadrature mixers and NCOs
Second-order resampling decimating CIC FIR filter
(rCIC2)
Fifth-order decimating CIC FIR filter (CIC5)
RAM coefficient decimating FIR filter (RCF)
Automatic gain control (AGC)
2× interpolation and channel interleave
ble channel multiplexing in the digital downconverter
ully utilize the AD6652’s capabilities.
re employed, the numb
ed due to the dual pr
CF stages to achieve demanding
n
ronization input pins allow startup,
a
N
ocessing require-
er of carriers that
nd
e
ated
ront
Rev. 0 | Page 24 of 76
ADC ARCHITECTU
The AD6652 front-end consists of two high performance, 12-bit
ADCs, preceded by differential sample-and-hold amplifiers
(SHA) that provide excellent SNR performance from dc to
200 MHz. A flexible, integrated voltage reference allows analog
inputs up to 2 V p-p. Each channel is equipped with an
overrange pin that toggles high whenever the analog input
exceeds the upper or lower reference voltage boundary. ADC
outputs are internally routed to the input matrix of the DDC
stage for channel distribution. The ADC data outputs are not
directly accessible to the user.
Each sample-and-hold amplifier (SHA) is followed by a pipe-
lined switched capacitor ADC. The pipelined ADC is divided
into three sections, consisting of a 4-bit first stage followed by
eight 1.5-bit stages and a final 3-bit flash. Each stage provides
sufficient overlap to correct for flash errors in the preceding
stages. The quantized outputs from each stage are combined
into a final 12-bit result in the digital correction logic. The
pipelined architecture permits the first stage to operate on a
new input sample while the remaining stages operate on the
preceding samples. Sampling occurs on the rising edge of the
clock.
Analog Input Operation
The analog inputs to the AD6652 are differential switched
capacitor SHAs that have been designed for optimum perform-
ance while processing differential input signals. The AD6652
accepts inputs over a wide common-mode range; however, an
input common-mode voltage V
recommended to maintain optimal performance and to
minimize signal-dependent errors.
Referring to Figure 38, the clock signal alternatively switches the
SHA between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can be
placed across the inputs to provide dynamic charging currents.
This passive network creates a low-pass filter at the ADC’s
input; therefore, the precise values are dependent upon the
application. In IF undersampling applications, any shunt capaci-
tors should be removed. In combination with the driving source
impedance, the shunt capacitors would limit the input
bandwidth.
RE
CM
, one-half of AVDD, is