AD6652BC/PCB Analog Devices Inc, AD6652BC/PCB Datasheet - Page 50

• Manufacturer Part Number: AD6652BC/PCB
• Description: BOARD EVAL W/AD6652 & SOFTWARE
• Manufacturer: Analog Devices Inc

Specifications of AD6652BC/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6652
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD6652
PARALLEL O
The AD6652 incorporates two independent 16-bit parallel po
for output data transfer. To minimize package ball count, the
eight LSBs of each 16-bit port are shared with their respective
DSP link port data bits (see Figure 54). This means that an
output port can transmit 16-bit parallel data or 8-bit link por
data, but not both. Transmitting both link and parallel data
simultaneously requires that the second AD6652 output port be
configured for that purpose.
Each parallel output port has six data sources routed to it (see
the Functional Block Diagram in Figure 1):
• Noninterpolated RAM coefficient FIR filter output data from
• Interpolated, interleaved, and/or AGC modified Chan
Channels 1, 2, 3, and 4
data
LINK PORT A CLOCK OUT
LINK PORT A CLOCK IN
LINK PORT A DATA OR 8 LSB'S
OF PARALLEL PORT A DATA
(SHARED PINS)
PCLK
PARALLEL PORT A MSB DATA
PARALLEL PORT A ACK
PARALLEL PORT A REQ
PARALLEL PORT A
CHANNEL INDICATOR
PARALLEL PORT A
I AND Q INDICATOR
LINK PORT B CLOCK OUT
LINK PORT B CLOCK IN
LINK PORT B DA
OF PARALLEL PORT B DATA
(SHARED PINS)
PCLK
PARALLEL PORT B MSB DATA
PARALLEL PORT B ACK
PARALLEL PORT B REQ
PA
CHANNEL INDICATOR
PARALLEL PORT B
I AND Q INDICATOR
Figure 54. Output Port Configuration
RALLEL PORT B
UTPUT PORTS
TA OR 8 LSB'S
/
/
/
/
/
/
8
8
2
8
8
2
nel A
Rev. 0 | Page 50 of 76
t
rts
• Interpolated, interleaved, and r AGC modified Channel B
Any of the six sources can
be configured to output parallel data or DSP link data. Out
port control registers (Table 29) perform these multiplexing and
selection tasks.
Parallel port configuration is specified by accessing Port
Control Register Addresses 0x1A and 0x1C for Parallel Ports A
and B, respectively. Port clo
the Master/Slave PCLK Modes section) is configured using t
port clock control register at Address 0x1E. Note that to acces
these registers, Bit 5 (access port control registers) of External
Address 3 (sleep register) must be set. The address is the
selected by programming the CAR register at External
Address 6.
The parallel ports are enabled by setting Bit 7 of the link contro
registers at Addresses 0x1B and 0x1D for Ports A and B,
respectively. Each parallel port is capable of operating in e
channel mode or AGC mode. These modes are described in
detail in the following sections.
CHANNEL MODE
Parallel port channel mode is selected by setting Bit 0 of
Addresses 0x1B and 0x1D for Parallel Ports A and B, respec-
tively. In channel mode, I and Q words from each channel are
directed to the parallel port, bypassing the AGC. The specific
channels output by the port are selected by setting Bits 1–4 of
Parallel Port Control Register 0x1A (Port A) and 0x1C (Port B).
Channel mode provides two data formats. Each format requires
a different number of parallel port clock (PCLK) cycles to
complete the transfer of data. In each case, each data element is
transferred during one PCLK cycle. See Figure 55 and Figure 56,
which present channel mode parallel port timing.
The 16-bit interle
output sample on back-to-back PCLK cycles. Both I and Q
words consist of the full port width of 16 bits. Data output
triggered on the rising edge of PCLK when both REQ and ACK
are asserted. I data is output during the first PCLK cycle; the
PAIQ and PBIQ output indicator pins are set high to indica
that I d
PCLK cycle; the PAIQ and PBIQ output indicator pins are low
durin this cycle.
data
g
ata is on the bus. Q data is output during the subsequent
aved format provides I and Q
be output on any port(s). A port can
ck master/slave mode (described in
/o
data for each
n
ither
put
is
te
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s
l