AD6652BC/PCB Analog Devices Inc, AD6652BC/PCB Datasheet - Page 23

• Manufacturer Part Number: AD6652BC/PCB
• Description: BOARD EVAL W/AD6652 & SOFTWARE
• Manufacturer: Analog Devices Inc

Specifications of AD6652BC/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6652
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TERMINOLOGY
Crosstalk
Coupling onto one channel being driven by a (−0.5 dBFS) signal
when the adjacent interfering channel is driven by a full-sc
signal. Measurement includes all spurs resulting from both
direct coupling and mixing components.
IF Sampling (Undersampling)
Due to the effects of aliasing, an ADC is not necessarily limited
to Nyquist sampling. Frequencies above Nyquist are aliased and
appear in the first Nyquist zone (dc to Sample Rate/2). Care
must be taken to limit the bandwidth of the sampled signal so
that it does not overlap Nyq
sam
S
more noise at higher input frequencies.)
Nyquist Samplin
Oversampling occu
analog input signal are be
and requires that the analo
two samples per cycle.
O
Out-of-range recovery time is th time it takes for the analog-
to-digital co
transient fro
negative full scale, or from 10% below negative full scale to 10%
below positive full scale.
Processing Gain
When the tuned channel occupies less bandwidth than the
input signal, this rejection of out-of-band noise is referred to as
processing gain. By using large decimation factors, this process-
ing gain can improve the SNR of the ADC by 20 dB or more.
The following equation can be used to estimate processing gain:
Signal-to-Noise Ratio (SNR)
The ratio of the rms value of the measured input signal to the
rms sum of all other spectral components within the pro-
grammed DDC filter bandwidth, excluding the first six
harmonics
de
Two-Tone IMD Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third-order intermodulation product; reported
in dBc.
HA (sample-and-hold amplifier) and clock jitter. (Jitter adds
ut-of-Range Recovery Time
cibels (dB).
pling performance is limited b
Processing
and dc. The value for SNR is expressed in
nverter (ADC) to reacquire the analog input
m 10% above positive full scale to 10% ab
_Gain
g (Oversamp
rs when the
=
10
low th
g inp
log
uist zones and alias onto itself. IF
⎡
⎢
⎣
ling)
frequen
ut frequency b
Filter
e Nyqu
e
Sample
y the bandwidth of the input
_
ist frequency (F
cy components o
Bandwidth
_
Rate
e sampled
2
⎤
⎥
⎦
ove
clo
f the
ck
at least
after a
/2),
ale
Rev. 0 | Page 23 of 76
ADC EQUIVALENT CIRCUITS
AVDD
AVDD
VDD
Figure 35. Analog Input Circuit
Figure 37. Digital Output
Figure 36. Digital Input
AD6652