AD6652BC/PCB Analog Devices Inc, AD6652BC/PCB Datasheet - Page 61

• Manufacturer Part Number: AD6652BC/PCB
• Description: BOARD EVAL W/AD6652 & SOFTWARE
• Manufacturer: Analog Devices Inc

Specifications of AD6652BC/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6652
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

M
chosen such that a
deta
0x9
Thi
The
The rCI
u
asso
Order R
0x92: rCIC2 Scale
The rCI
co
zation of the data from the floating-point input. The use of this
sc
the Second-Order RCIC Filter section.
Bit 11 is reserved. Write all bits to Logic 0.
Bit 10 is reserved. Write all bits to Logic 0.
Bits 9–5 are the actual scale value used when the level indicato
LI pin associated with this channel, is active (Logic 1).
Bits 4–0 are the actual scale value used when the level indic
LI pin associated with this channel, is inactive (Logic 0).
0x93: Reserved
Eight bits, reserved (must be written low).
0x94: CIC5 Decimation – 1 (M
This register is used to set the decimation in the CIC5 filter. The
8-bit value written to this register is the decimation minus 1.
0x95: CIC5 Scale
The 5-bit CIC5 scale factor is used to compens
growth of the CIC5 filter. For details, see the Fi
Filter section.
Reserved (must be written low).
0x97–0x9F: Unused
Unused.
0xA0: RCF Decimation − 1 (M
This register is used to set the decimation of the RCF stage. Th
value written to this register is the desired decimation mi
one. Although this is an 8-bit register that allows decimation u
to 256, most filter designs should be limited to between 1 an
32. Higher decimations are allowed, but the alias rejection of the
RCF might not be acceptable for some applications.
0xA1: RCF Decimation Phase (P
This register allows any one of the M
used and can be adjusted dynamically. Each time a filter is
started, this phase is updated. When a chann
0x96: Reserved
pon the decimation o he rCIC2. There is no timing error
ale register is influenced by the rCIC2 growth. For details, see
rCIC2
mpensate for the gai of the rCIC2 and to adjust the linea i-
s register is used to
1: rCIC2 Interpol
ils, see the Second
ciated with this in
value written to th
must be chosen larger than L
C2 interpolation can range from 1 to 512, dependin
C2 scale regist is used to provide attenuation to
CIC Filter sect
suit
terpolation. For deta
-Order RCIC Filter s
er
able rCIC2
ation − 1 (L
f t
n
ion.
is register is the interpolation m
set the interpol
RCF
CIC5
scalar can be chosen. For
rCIC2
RCF
rCIC2
− 1)
− 1)
RCF
)
ation in the rCIC2 fil
, and both must be
− 1
phases of the filter to
ils, see the Secon
ection.
)
el is synchronized,
ate for the
fth-Order CIC
inus
nus
ter.
d-
ator,
g
1.
r
d
Rev. 0 | Page 61 of 76
be
r,
p
e
it retains the phase setting chosen here. This can be used as part
of
al
p
0
The numbe
re
0xA3: RCF Coeffici
T
co
among mult
re
T
(from the shadow register) on every new filter output sample.
This allows the coefficient offset to be written without
disturbing operation, even while a filter is being computed. Th
next sample that comes out of the RCF is
0xA4: RCF Control Register
The RCF control register is an 11-bit register that controls the
general features of the RCF as well as output formatting. The
bits of this register and their functions are described below.
Bit 10 bypa
the BIST-I and BIST-Q registers. The 16 MSBs of the CIC5 data
can be accessed from this register, if Bit 9 of the output con
register at Channel Address 0xA9 is set.
Bit 9 of this register
RCF. If this bit is 0, then the RCF
own channel. If this bit is 1, then i
CIC5 of another channel. The CIC5 channels that the RCF c
be connected to when this bit is 1 are shown in the Table 26.
These can be us
process wider bandwidth channels
Table 26. RCF Input Configurations
Channel
0
1
2
3
Bit 8 is used as an extra address to allow a second block of
128 words of CMEM to be addressed by the channel addres
at 0x00–0x7F. If this bit is 0, then
if this bit is 1, then the next 128 words are written. This bit is
used to program only the coefficient memory so that filters
longer than 128 taps can be realized.
Bit 7 is used to control the output formatting of the AD6652’s
RCF data. This bit is used only when the 8 + 4 or 12 + 4
floating-point modes are c
Bits 5 and 4 of this register. When this bit is 0, then the I and Q
output exponents are determined separately based on their
air. For details, see the RAM Coefficien
xA2: RC Number of Tap – 1 (N
his reg
his reg
low m
gist
fere
efficien memory is used for a filter. It can be used t
a timing rec
er.
nced b
ulti
iste
iste
t
F
ple RCFs to work together wh
sses the RCF filter and sends the CIC5 output data to
r of taps for the RCF filter mi
r is used to specify which sec
r is shadowed, and the filter po
iple filters that are loaded in
y this pointer.
overy loop with an external processor or can
ed to allow multiple RCFs to be used together to
RCF Input Source when Bit 9 Is 1
1
0
1
1
controls the source of the input data to the
ent Offset (CO
hosen. These modes are enabled by
processes the output data of its
the first 128 words are written;
t processes the data from the
.
RCF
RCF
− 1)
)
to memory and
t Filter section.
tion of the 256-word
nus 1 is written to this
ile using a single RCF
with the new filter.
inter is updated
AD6652
o select
trol
ses
an
e