AD6652BC/PCB Analog Devices Inc, AD6652BC/PCB Datasheet - Page 69

• Manufacturer Part Number: AD6652BC/PCB
• Description: BOARD EVAL W/AD6652 & SOFTWARE
• Manufacturer: Analog Devices Inc

Specifications of AD6652BC/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6652
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

If this bit is set, only the f
succeeding sync events are ignored until Bit 1 is reset.
Bit 0 is used to bypass the AGC section, when it is set. When the
AGC is bypassed, the output data is the 16 MSBs of the 24-bit
input data from the half-band filter.
0x13: AGC B Hold-Off Counter
The AGC B hold-off counter is loaded with the 16-bit value
written to this address when Sync Now is written high or a
Pin_Sync signal is receiv
AGC cannot be synchr
Note: The
a
intends to use AGC A’s hold-off counter, the user must either
attach the external sync signal to the pin sync that is assign
DDC Channel 2, or use the software-controlled sync now
function of Bit 3 at 0x12.
The hold-off counter must be p
numb
decimated value is updated. Writing a logic high to the pro
pin sync pin triggers the AGC hold-off counter with a retri
able one-shot puls
0x14: AGC B Desired Level
This 8-bit register contains the desired output power level or
desired clipping level, dependi
This desired reques
in steps of 0.094 dB. An 8-bit
tion is used with a 2-bit exponent followed
tissa. The mantissa is in st
6.02 dB steps. For example: 10’10
0.094 = 15.518 dB.
0x15: AGC B Signal Gain
This register is used to set t
in the gain multiplier.
g
b
nent followed by the 8-bit mantissa. For example:
0111’10001001 represents 7 × 6.02 + 137 × 0.024 = 45.428 dB.
0
T
value can be set from 0 to 0.996 in steps of 0.0039. This value of
K is updated in the AGC loop each time the AGC is initialized.
0x17: AGC B Pole Location
This 8-bit register is used to define the open loop filter pole
location P. Its value can be set from 0 to 0.996 in steps of 0.0039.
This value of P is updated in the AGC loop each time the AGC
is initialized. This open loop pole location directly impacts the
closed loop pole locations as explained in the Automatic Gain
Control section.
ssigned to
ain between 0 dB and 96.296
inary floating-point representation is used with a 4-bit expo-
x16: AGC B Loop Gain
his 8-bit register is used to define the open loop gain K. Its
er that corresponds to the
hold-off counter of AGC B shares the pin
DDC processing Channel 2. Therefore, if the user
e every time the pin is written high.
t R level can be set from 0 dB to −23.99 dB
This
onized.
ed. If this register is written to 0, the
irst sync high is recognized and
eps of 0.094 dB
h
12-bit value sets the initial signal
e initial value for a signal gain used
binary floating-point representa-
ng on the mode of operation.
dB in steps of 0.024 dB. A 12-bit
rogrammed with a 16-bit
desired delay before a new CIC
0101 represents 2 × 6.02 + 37 ×
and the exponent is in
by the 6-bit man-
sync
per
gger-
ed to
Rev. 0 | Page 69 of 76
0x18: AGC B Average S
This 6-bit register contains the scale used for the CIC filter and
the number of power samples to be averaged before being fed to
the CIC filter.
Bits 5–2 define the scale used for the CIC filter.
Bits 1–0 define the number of samples to be averaged before
they are sent to the CIC decimating filter. This number can be
set between 1 and 4 with bit representation 00 meaning one
sample and bit representation 11 meaning four samples.
0x19: AGC B Update Decimation
This 12-bit register sets the AGC decimation ra
4096. Set an appropriate scaling factor to avoid loss of bits.
0x1A: Parallel Port Control A
Data is out
por
disabled and the use of Parallel Port A is enabled. The parallel
port provides different data modes for interfacing with DS
FPGAs.
Bit 0 selects which data is output
Bit 0 = 0, Parallel Port A outputs data from the RCF according
to the format specified
Port A outputs the data from the AGCs
specified by Bits 1 and 2
In AGC mode, Bit 0 = 1 and B
can output data f
can output data from AGC B
the rate of triggers from each AGC, which in turn is determined
by the decimation rate of the channels feeding it. In channel
mode, Bit 0 = 0 and Bits 1–4 determ
the four processing channels is o
depends on the rate of triggers rece
which is determined by the decim
The channel output indicator pins can
which data came from which channel.
Bit 5 determines the format of the output data words. When
Bit 5 = 0, Parallel Port A outputs 16-bit words on its 16-bit bus.
This means that I and Q data are interleaved, and the IQ
indicator pin determines whether data on the port is I data or
Q data. When Bit 5 = 1, Parallel Port A is outputting an 8-bit
I word and an 8-bit Q word at the same time, and the IQ
indicator pins are high.
0x1B: Link Port Control A
Data is output through either a parallel port interface or a link
port interface. The link port provides an efficient data link
between the AD6652 and a TigerSHARC DSP and can be
enabled by setting 0x1D, Bit 7 = 1.
t interf
ace. When 0x1B, Bit 7 = 0, the use of Link Port A is
put through either a parallel port interface or a link
rom AGC A.
by Bits 1–4. When Bit 0 = 1, Parallel
.
amples
. The order of output depends on
it 1 determines if Parallel Port A
Bit 2 determines if Parallel Port A
utp
on Parallel Port A. When
a
tion rate of each channel.
ived from each channel,
ut. The output order
ine which combination of
be used to determine
according to the format
tio from 1 to
AD6652
Ps or