AD6652BC/PCB Analog Devices Inc, AD6652BC/PCB Datasheet - Page 47

• Manufacturer Part Number: AD6652BC/PCB
• Description: BOARD EVAL W/AD6652 & SOFTWARE
• Manufacturer: Analog Devices Inc

Specifications of AD6652BC/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6652
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Start with Soft Sync
The AD6652 includes the ability to synchronize channels or
chips using the microport. One action to synchronize is the
start of channels or chips. The start update hold-off counter
(0x83) in conjunction with the start bit and sync bit (External
Address 5) allows this synchronization. The start update hold-
off counter delays the start of a channel by the 16-bit value
programmed at 0x83 (number of AD6652 CLK periods Use
the following me
channels via microprocessor control:
1.
2.
AD6652 HARDWARE AND SOFTWARE SYNC
CONTROL FOR ONE PROCESSING CHANNEL
SYNCA PIN
SYNCB PIN
SYNCC PIN
SYNCD PIN
* FROM EXTERNAL MEMORY ADDRESS REGISTER 4:3-0
NOTE: ALL CIRCUITRY AND SIGNALS ARE IDENTICAL AND REPEATED FOR
EACH CHANNEL EXCEPT SOFT SYNCx. SOFT SYNCx CONTROL SIGNALS
ARE ASSIGNED TO A SINGLE CHANNEL AND ARE NOT SHARED WITH ANY
OTHER CHANNEL.
Place the channels in sleep mode (a hard
AD6652 RESET pin forces all four DDC processing
channels into sleep mode).
Write the start hold-off counter(s) (0x83) to a value from 1
to 2
programmed, write all other registers now.
16
PIN SYNC_EN A*
PIN SYNC_EN B*
PIN SYNC_EN C*
PIN SYNC_EN D*
− 1. If the chip or channels have not been completely
thod to synchronize the start of
Figure 53. Synchronizing Signal Routing Example, Channel 0 ;
either a Pin_Sync or a Soft_Sync Signal to Be Routed
reset to the
multiple
START SYNC ENABLE, 0x82:0 AND EXT ADD 4:4
HOP SYNC ENABLE, 0x82:1 AN
).
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SYNC
SY
SYNCC
SYNCD
SYNCA
SYNCB
SYNCC
SYNCD
0x88:8
0x88:7
0x88:8
0x88:7
NCB
A
Note that Multiple Qualifiers Are Required to Enable
D EXT ADD 4:5
3.
Note: Each channel has a redundant soft-sync control register
Address 0x81. This register mimics the programming as set in
the External Memory Address 5:5–4. The user can control the
soft-sync function of a DDC channel by writing to the 0x81
register, if it is adva
The time from when the DTACK
acknowledges t
when the DDC channel begins processing data is equal to the
time period set up by the start hold-off counter value at 0x83
plus six CLK cycles.
SELECT LINES
FROM NCO
CONTROL REGISTER
SELECT LINES
FROM NCO
CONTROL REGISTER
to a Hop or Start Hold-Off Counter
MULTIPLEXER
MULTIPLEXER
CHANNEL 0
CHANNEL 0
Write the start bit and the applicable channel sync bit(s)
high at External Address 5. This triggers the start hold-off
counters to begin their count. The counters ar
with the AD6652 CLK signal. When it reaches a count of
one, the sleep bits of the selected channels are set low to
turn on the channel with the new or existing operating
parameters.
START
SYNC
SYNC
HOP
he receipt of the soft sync command
ntageous to do so in the application.
START EXT ADD 5:4
SOFT SYNC0 EXT ADD 5:0
HOP EXT ADD 5:5
SOFT SYNC0 EXT ADD 5:0
pin goes high (which
TO START HOLD-OFF COUN
TO NCO HOLD-OFF COUNT
e clocked
data) to
AD6652
ER
TER
at