AD6652BC/PCB Analog Devices Inc, AD6652BC/PCB Datasheet - Page 8

• Manufacturer Part Number: AD6652BC/PCB
• Description: BOARD EVAL W/AD6652 & SOFTWARE
• Manufacturer: Analog Devices Inc

Specifications of AD6652BC/PCB

• Module/board Type: Evaluation Board
• For Use With/related Products: AD6652
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD6652
GENERAL TIMING CHARACTERISTICS
All timing specifications valid over VDD range of 2.25 V to 2.75 V and VDDIO range of 3.0 V to 3.6 V.
CLOAD = 40 pF on all outputs, unless otherwise specified.
Table 6.
Parameter (Conditions)
CLK TIMING REQUIREMENTS
RESET TIMING REQUIREMENTS
LEVEL INDICATOR OUTPUT SWITCHING CHARACTERISTICS
SYNC TIMING REQUIREMENTS
PARALLEL PORT TIMING REQUIREMENTS (MASTER MODE)
PARALLEL PORT TIMING REQUIREMENTS (SLAVE MODE)
LINK PORT TIMING REQUIREMENTS
1
The timing parameters for Px[15:0], PxREQ, and PxACK apply for Port A and B (x stands for A or B).
Switching Characteristics
Input Characteristics
Switching Characteristics
Input Characteristics
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CLK
CLKL
CLKH
RESL
DLI
SS
HS
DPOCLKL
DPOCLKLL
DPREQ
DPP
SPA
HPA
POCLK
POCLKL
POCLKH
DPREQ
DPP
SPA
HPA
RDLCLK
FDLCLK
RLCLKDAT
FLCLKDAT
CLK Period
CLK Width Low
CLK Width High
RESET Width Low
↑CLK to LI (LIA, LIA; LIB, LIB) Output Delay Time
SYNC(A,B,C,D) to ↑CLK Setup Time
SYNC(A,B,C,D) to ↑CLK Hold Time
↓CLK to ↑PCLK Delay (Divide-by-1)
↓CLK to ↑PCLK Delay (Divide-by-2, -4, or -8)
↑PCLK to ↑PxREQ Delay
↑PCLK to Px[15:0] Delay
PxACK to ↓PCLK Setup Time
PxACK to ↓PCLK Hold Time
PCLK Period
PCLK Low Period (when PCLK Divisor = 1)
PCLK High Period (when PCLK Divisor = 1)
↑PCLK to ↑PxREQ Delay
↑PCLK to Px[15:0] Delay
PxACK to ↓PCLK Setup Time
PxACK to ↓PCLK Hold Time
↑PCLK to ↑LxCLKOUT Delay
↓PCLK to ↓LxCLKOUT Delay
↑LCLKOUT to Lx[7:0] Delay
↓LCLKOUT to Lx[7:0] Delay
1
1
1
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Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
15.4
6.2
6.2
30.0
3.3
2.0
1.0
6.5
8.3
12.5
2.0
2.0
1.0
1.0
0
0
Min
7.0
−3.0
Typ
0.5 × t
0.5 × t
t
t
CLK
CLK
/2
/2
POCLK
POCLK
Max
10.0
10.5
14.6
1.0
0.0
10.0
11.0
2.5
0
2.9
2.2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns